Browse Prior Art Database

MACROCELL ARRAY HAVING MIXED SINGLE AND DOUBLE DRIVE

IP.com Disclosure Number: IPCOM000005600D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2001-Oct-18
Document File: 2 page(s) / 61K

Publishing Venue

Motorola

Related People

Steve Lai: AUTHOR

Abstract

Existing CMOS gate arrays having a plurality of semiconductor devices within a plurality of cells use a single drive level for the cells resulting in the drive level being either too high or too low for many situations. A typical cell consists of two P-channel and two N-channel transistors, resulting in asingle two-input logic gate.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 70% of the total text.

Page 1 of 2

MOTOROLA Technical Developments Volume 6 October 1986

MACROCELL ARRAY HAVING MIXED SINGLE AND DOUBLE DRIVE

by Steve Lai

   Existing CMOS gate arrays having a plurality of semiconductor devices within a plurality of cells use a single drive level for the cells resulting in the drive level being either too high or too low for many situations. A typical cell consists of two P-channel and two N-channel transistors, resulting in asingle two-input logic gate.

   The gate array described herein utilizes a cell having a double channel configuration, which with proper choice of device sizes allows for efficient layout of cells with different drive capabilities. The new gate array cells comprise transistors, about half the size of the optimum sizes of existing gate arrays, in a 2 (2 P-channel and 2 N-channel) configuration as shown in the figure.

   To obtain the equivalent drive of existing cells, the transistors may be connected in parallel. To obtain a high density device, the transistors may be used individually, resulting in two two-input gates for each cell, thereby doubling the gate counts from existing gate arrays, Furthermore, eight small transistors in the new cell instead of four large transistors in the existing cell will allow more flexible and efficient circuit layout.

   Extra space required by the new cell transistor layout will be compensated for by allowing only minimum interconnect space in the cell. External tracts in the area surrounding the cell may be used for i...