Browse Prior Art Database

TIMING GENERATOR

IP.com Disclosure Number: IPCOM000005608D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2001-Oct-18
Document File: 2 page(s) / 65K

Publishing Venue

Motorola

Related People

Hiroshi Sakamoto: AUTHOR

Abstract

The circuit of Fig. 1 is designed to generate an output signal VO whose leading and trailing edges appear after predetermined two separate period of time Tl and T2, with respect to the transient timings of an input signal Vi.

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cm MOlOROLA Technical Developments Volume 6 October 1986

TIMING GENERATOR

by Hiroshi Sakamoto

   The circuit of Fig. 1 is designed to generate an output signal VO whose leading and trailing edges appear after predetermined two separate period of time Tl and T2, with respect to the transient timings of an input signal Vi.

   In a conventional timing generator which does not include circuit portion surrounded by dotted line, if the switching frequency of the input signal Vi is high, or if the pulse width of the input signal Vi is short, capacitor G is not fully charged to BDD or not fully discharged to GND, in response to the leading or trailing edge of the input signal Vi. Therefore, the time periods Tl and/or T2 cannot be accurate.

   This problem can be solved by adding a pair of switches SW2 and SW3 controlled by the existing output VO from voltage comparator CMP, as illustrated in Fig. 1. During the capacitor charge time, from GND to Vref, the charge timing is controlled by G and the current of a current source I1 as illustrated in Fig. 2. As soon as the capacitor voltage becomes larger than Vref, the output VO of the comparator CMP becomes high so that the switch SW2 is turned on and the capacitor voltage is pulled up to VDD. On the other hand, during discharge, the discharge timing is controlled by C and the current of a current source 12. When the capacitorvoltage becomes less than Vref, the output VO becomes low. At this time, another switch SW3 is turned on and th...