Browse Prior Art Database

MICROPROCESSOR ARCHITECTURE

IP.com Disclosure Number: IPCOM000005616D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2001-Oct-19
Document File: 3 page(s) / 93K

Publishing Venue

Motorola

Related People

Kuppuswamy Raghunathan: AUTHOR [+3]

Abstract

The architecture of the MC68HCll family of CMOS microcomputers provides high throughput with fewer internal busses. The use of fewer internal busses reduces the number of register transfer signals and reduces the current which is required for the internal busses. The improvement is due largely to judiciously placed transfers, bi-directional transfers, a pre-charged bus which can be used on either phase of the system clock and direct accumulator transfers to the ALU.

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MOTOROLA Technical Developments Volume 6 October 1986

MICROPROCESSOR ARCHITECTURE

by Kuppuswamy Raghunathan, Robert J. Skruhak and Herchel A. Vaughn

   The architecture of the MC68HCll family of CMOS microcomputers provides high throughput with fewer internal busses. The use of fewer internal busses reduces the number of register transfer signals and reduces the current which is required for the internal busses. The improvement is due largely to judiciously placed transfers, bi-directional transfers, a pre-charged bus which can be used on either phase of the system clock and direct accumulator transfers to the ALU.

   FIG. 1 illustrates the architecture of the execution unit of the MC68HCll microcomputer. Accumulators A and B (ACCA and ACCB, respectively) have direct transfer paths to the A input of the ALU. In addition, both accumulators have bi-directional transfer paths to the internal busses DB and TXB. This scheme allows an ALU operation on an accumulator via the TXB bus, for example, while the DB bus is being used for a different data transfer. This provides for high throughput with only two data busses.

   Transfers to the INX bus (INXH and INXL) may occur on either phase 1 or phase 2 of the system clock. Both of these busses are pre-charged and the pre-charge devices remain active unless either the incrementor (INCRH and INCRL) or another bus is coupled to the pre-charged bus. When reading a register directly onto the INXH or INXL bus (on phase l), the bus during the pre...