Browse Prior Art Database

LOGICAL TO PHYSICAL ADDRESS CONVERSION

IP.com Disclosure Number: IPCOM000005617D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2001-Oct-19
Document File: 3 page(s) / 89K

Publishing Venue

Motorola

Related People

Joseph Gergen: AUTHOR [+2]

Abstract

This article discusses a technique for logical to physical address conversion for a RAM-based, variable length, circular queue in a Finite Impulse Response (FIR) filter structure.

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MOTOROLA Technical Developments Volume 6 October 1986

LOGICAL TO PHYSICAL ADDRESS CONVERSION

by Joseph Gergen and Charles Thompson

This article discusses a technique for logical to physical address conversion for a RAM-based, variable length, circular queue in a Finite Impulse Response (FIR) filter structure.

   The use of a circular queue is a practical way to implement a shift register. A circular queue is easily con- structed using a RAM and a pointer. When simulating a shift register, the physical location of the first shift register tap, logical address 0, can vary. Thus, it is useful to provide an address translation unit which can con- vert a logical address number (such as a desired filter tap) to its corresponding physical address within the RAM. This article discusses a unit which will convert a logical address to a physical RAM address within the circular queue, and will also allow the user to address unused taps if the size of the RAM is greater than the size of the circular queue.

   The addressing unit converts a logical address from the user to the actual physical storage address within the RAM. Consider a RAM partitioned as in FIG. 1. When addressing into locations above the circular queue, the logical and physical addresses are the same. If the logical address falls within the circular queue, however, an address conversion must be performed. This conversion can be performed via an adder shown in FIG. 2, or can be done as shown in FIG. 3 with adown counter, which d...