Browse Prior Art Database

BASIC BARREL SHIFTER ALGORITHMS

IP.com Disclosure Number: IPCOM000005619D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2001-Oct-19
Document File: 1 page(s) / 78K

Publishing Venue

Motorola

Related People

Dave Mothersole: AUTHOR [+2]

Abstract

Todays 32.bit architectures have been crafted to include a full compliment of instructions that deal with the manipulation of bit operands and fields. These instructions include some operations that are not easily implemented to yield both performance and reasonable cost. Examples of these operations include bit opera- tions such as arithmetic and logical shifting, bit rotating, bit manipulation and bitfield manipulation, and multi- ply/divide. The MC66020 32.bit processor utilizes a unique set of algorithms to facilitate optimal performance of the above operations while maintaining a reasonable implementation cost. The algorithms require the use of several key mechanisms such as a32-bit barrel shifter, a pair of source and destination registers, and acom- plex pipelined control mechanism. These algorithms together with the above hardware allow most bit opera- tions to be performed in a single operation cycle as opposed to the traditional serial shift mechanism where the performance is determined by the number of bits in the field or the number of bit positions the operation entails. These algorithms have been expanded to allow the multiply instructions to include a fast scanning of overlapping fields of bits in the multiplicand.

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0 M MOWROLA

Technical Developments Volume 6 October 1966

BASIC BARREL SHIFTER ALGORITHMS

by Dave Mothersole and Bill Moyer

   Todays 32.bit architectures have been crafted to include a full compliment of instructions that deal with the manipulation of bit operands and fields. These instructions include some operations that are not easily implemented to yield both performance and reasonable cost. Examples of these operations include bit opera- tions such as arithmetic and logical shifting, bit rotating, bit manipulation and bitfield manipulation, and multi- ply/divide. The MC66020 32.bit processor utilizes a unique set of algorithms to facilitate optimal performance of the above operations while maintaining a reasonable implementation cost. The algorithms require the use of several key mechanisms such as a32-bit barrel shifter, a pair of source and destination registers, and acom- plex pipelined control mechanism. These algorithms together with the above hardware allow most bit opera- tions to be performed in a single operation cycle as opposed to the traditional serial shift mechanism where the performance is determined by the number of bits in the field or the number of bit positions the operation entails. These algorithms have been expanded to allow the multiply instructions to include a fast scanning of overlapping fields of bits in the multiplicand.

The algorithms involve the use of the above hardware to shift or rotate or extract and insert fields of bits. In order to understand the algorithms, it is necessary to first define the basic hardware mechanisms required.

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SLIITCH GHRREL SHIFTER

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32

Shifter Block Diagram

   The REG A and REG B blocks are 32.bit registers which are used to hold the source operand and the result of the operation. The SWITCH block is a field selector for operations to and from REG A, since some operations use less than 32.bit fields. The BARREL...