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DATA CACHE LOAD INHIBIT ATTRIBUTE STORED IN TRANSLATION TABLES

IP.com Disclosure Number: IPCOM000005622D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2001-Oct-22
Document File: 1 page(s) / 84K

Publishing Venue

Motorola

Related People

Brad Cohen: AUTHOR

Abstract

A fundamental concern in data cache design is insuring that the data stored in the cache is "up to date." The contents of a main memory location, which is stored in the data cache, may be altered, such that the cache no longer reflects the value stored in the main memory location. The cache then contains what is termed "stale data:'This phenomenon commonly occurs in areas of inter-cpu communication (mailboxes or semaphore loca- tions) or in areas which will experience DMA activity, Stale data is a problem to be avoided in any data cache, but is more severe in logical bus data caches. Physical data caches which implement stale data invalidation schemes first detect physical memory writes, then invalidate any stored entries which correspond to the written main memory locations. Main memory resides on the physical bus, thus in addition to the detection/invalidation of a physical data cache, control circuitry for a logical data cache must obtain the (all) inverse mapping(s) associated with the physical location which is altered, to determine which logical address location(s) in the cache to invalidate.

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m MO7VROLA Technical Developments October 1986

DATA CACHE LOAD INHIBIT ATTRIBUTE STORED IN TRANSLATION TABLES

by Brad Cohen

   A fundamental concern in data cache design is insuring that the data stored in the cache is "up to date." The contents of a main memory location, which is stored in the data cache, may be altered, such that the cache no longer reflects the value stored in the main memory location. The cache then contains what is termed "stale data:'This phenomenon commonly occurs in areas of inter-cpu communication (mailboxes or semaphore loca- tions) or in areas which will experience DMA activity,

   Stale data is a problem to be avoided in any data cache, but is more severe in logical bus data caches. Physical data caches which implement stale data invalidation schemes first detect physical memory writes, then invalidate any stored entries which correspond to the written main memory locations. Main memory resides on the physical bus, thus in addition to the detection/invalidation of a physical data cache, control circuitry for a logical data cache must obtain the (all) inverse mapping(s) associated with the physical location which is altered, to determine which logical address location(s) in the cache to invalidate.

   An alternative solution is to avoid the detection, inverse mapping, and invalidation problems altogether by declaring areas of memory which may be shared by other DMA devices non-cacheable. This eliminates the need for a detect and invalidate scheme by preventing the shared locations from ever being loaded into the cache. The problem with this scheme is how to provide the mechanism for efficiently signaling the data cache that entries should not be loaded. The ideal solution would have a "one time" declaration of whether the memory space is cacheable, by the operating system, followed by the automatic execution of this declaration. Note also that an appropriate time for the cacheablity declaration is at the time memory space for a process is allocated.

   Existing operating systems have schemes implemented which allow a translation descriptor with a non- cacheable attribute to be loaded in...