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A HIGH YIELD OPTOELECTRONIC WAFER PROCESS

IP.com Disclosure Number: IPCOM000005626D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2001-Oct-22
Document File: 2 page(s) / 92K

Publishing Venue

Motorola

Related People

Neal Mellen: AUTHOR [+2]

Abstract

A significant problem in the fabrication of InGaAsP and AlGaAs LEDs is the breakage of wafers during processing because of the fragility of III-V compounds. The problem becomes more severe after the wafer is lapped and polished to the desired thickness (3-4 mils for some devices). Submounts have been used previous- ly to minimize breakage with some success. These submounts have always been removed at a later point in the process resulting in subsequent handling of thin wafers. The technique described below minimizes wafer breakage by permanently bonding asubmount to the wafer before the wafer is thinned, thus, eliminating handl- ing of the wafer directly when it is the most fragile. This technique is applicable whenever the thermal conduc- tivity loss due to the submount is either negligible compared to the package thermal conductivity or when the die heat dissipation is not a major concern for device operation or reliability.

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MOTOROLA Technical Developments Volume 6 October 1966

A HIGH YIELD OPTOELECTRONIC WAFER PROCESS

by Neal Mellen and Diana Convey

   A significant problem in the fabrication of InGaAsP and AlGaAs LEDs is the breakage of wafers during processing because of the fragility of III-V compounds. The problem becomes more severe after the wafer is lapped and polished to the desired thickness (3-4 mils for some devices). Submounts have been used previous- ly to minimize breakage with some success. These submounts have always been removed at a later point in the process resulting in subsequent handling of thin wafers. The technique described below minimizes wafer breakage by permanently bonding asubmount to the wafer before the wafer is thinned, thus, eliminating handl- ing of the wafer directly when it is the most fragile. This technique is applicable whenever the thermal conduc- tivity loss due to the submount is either negligible compared to the package thermal conductivity or when the die heat dissipation is not a major concern for device operation or reliability.

   The process is shown schematically in Figure 1. The specific process outlined is for an InGaAsP LED wafer but in general may be applied to LEDs, lasers and other devices which require a thin or delicate wafer or a front- to-back alignment. Steps l-6 are typical for a standard surface emitting InGaAsP LED. The first step of the pro- cess is to deposit the dielectric and define the p-side contact hole. The wafer is then prepared for a lift-off and the p-metal is deposited. The process shown is for a front-to-back alignment using an IR aligner in the trans- mitted light mode; if the reflected light mode of the aligner is used this lift-off step is not necessary.

   Photoresist is again applied and is aligned to the same grid pattern as in the p-metal lift-off to serve as a plating mask. Heatsinks are then plated and the p-metal is lifted off. The grid pattern which now remains is transparent to IR...