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AN IMPROVED SIDEWALL BASE CONTACT TRANSISTOR

IP.com Disclosure Number: IPCOM000005629D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2001-Oct-22
Document File: 2 page(s) / 75K

Publishing Venue

Motorola

Related People

Gary J. Seiter: AUTHOR

Abstract

Advanced sidewall base contact bipolar transistors can be improved by utilizing a silicon-on-insulator (SOI) process. This process will eliminate all collector-substrata junction capacitance and thus improve device performance.

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MOlVROLA Technical Developments Volume 7 October 1987

AN IMPROVED SIDEWALL BASE CONTACT TRANSISTOR

by Gary J. Seiter

ABSTRACT

   Advanced sidewall base contact bipolar transistors can be improved by utilizing a silicon-on-insulator (SOI) process. This process will eliminate all collector-substrata junction capacitance and thus improve device performance.

INTRODUCTION

   It is well known that the parasitic resistances and capacitances of conventional bipolar transistors leads to the degradation of high-speed operation. These parasitic elements are associated with the extrinsic regions of the device. Recent process developments are intended to reduce these extrinsic regions. One popular pro- cess is the self-aligned sidewall base contact bipolar structure. See Figure 1. This structure utilizes sidewall base contacts 10 to minimize the parasitic base-collector diode junction capacitance by introducing an insulating oxide 11 between the extrinsic base 12 and the extrinsic collector 13 regions. In this device, the active transistor region is fabricated in epitaxial silicon 14 which is grown over the buried layer 15. This buried layer has been previously defined in the substrate 16.

DISCUSSION

   An improvement to this structure would be to fabricate the device on a N+ substrate layer 17 which has previously undergone processing to form a buried Si02 insulating layer 18 beneath it. This insulating layer could be produced by the ion implantation of 02 followed by an appropriate...