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USING BITS IN AN OPCODE TO SPECIFY WHAT TO INVALIDATE IN A CACHE

IP.com Disclosure Number: IPCOM000005630D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2001-Oct-22
Document File: 2 page(s) / 108K

Publishing Venue

Motorola

Related People

Ralph McGarity: AUTHOR [+2]

Abstract

Thedesign of the MC68851 Paged Memory Management Unit contains an Address Translation Cache that stores recently used logical to physical address translations. For various reasons, the data that is stored in this cache can become out of date. An example is the fixing of a page fault by an operating system. The operating system brings the page of data from a disk to main memory, but the cache may still contain information in- dicating that the page is out on the disk. The old information must be removed from the cache. One way of guaranteeing that the old information is removed from the cache is to invalidate all of entries in the cache. Due to the large size of the cache in the MC68851, we decided that it would cost too much in terms of time to refill the entire cache when all that was required was the removal of one entry.

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MOTOROLA Technical Developments October 1987

USING BITS IN AN OPCODE TO SPECIFY WHAT TO INVALIDATE IN A CACHE

by Ralph McGarity and Michael Cruess

Microprocessor Products Group

    Thedesign of the MC68851 Paged Memory Management Unit contains an Address Translation Cache that stores recently used logical to physical address translations. For various reasons, the data that is stored in this cache can become out of date. An example is the fixing of a page fault by an operating system. The operating system brings the page of data from a disk to main memory, but the cache may still contain information in- dicating that the page is out on the disk. The old information must be removed from the cache. One way of guaranteeing that the old information is removed from the cache is to invalidate all of entries in the cache. Due to the large size of the cache in the MC68851, we decided that it would cost too much in terms of time to refill the entire cache when all that was required was the removal of one entry.

   Since the MC88851 was being designed with a coprocessor interface, we began looking at various ways to specify which entries to invalidate in the Address Translation Cache. A scheme involving the use of one or more control registers for the cache could have been implemented. This type of mechanism would have re- quired the software to use several instructions to invalidate the entry or entries that had to be removed. In addi- tion, it would have required more interaction between the main processor and the MC68851 coprocessor. This would have been slower.

   The solution for the problems was to encode the specification of which cache entries to invalidate in the coprocessor command word of the coprocessor instruction. The command word of a coprocessor instruction is always passed to the coprocessor, and bits in the command word of the MC68851 were available. The only additional data that is required for specifying which entries to invalidate is an address. This is specified by the effective address bits of the coprocessor instruction, along with any required extension words. Using the effective address in this way allows us to take advantage of the effective address calculation abilities of the processor to increase the flexibility in specifying addresses.

   The exact format of the command word is shown in Figure 1. It allows a single instruction to invalidate all of the cache entries, only the entries that have specific function code or codes, or a single entry in the cache. (The items that mention Shared entries allow for the invalidation of special entries in the Address Translation Cache that would otherwise not be invalidated). This arrangement provides great flexibility to the software in invalidati...