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Method for a partitioned capacitor in BBUL for chipset and non-CPU applications

IP.com Disclosure Number: IPCOM000005651D
Publication Date: 2001-Oct-23
Document File: 3 page(s) / 1K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a partitioned capacitor in bumpless build-up layer (BBUL) technology for chipset and non-CPU applications. Benefits include improved placement, reduced inductance, and improved capacitance of bypassing capacitors and processors, and an improved method for meeting multiple-voltage requirements of a chipset or non-CPU I/O power delivery system.

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Method for a partitioned capacitor in BBUL for chipset and non-CPU applications

Disclosed is a method for a partitioned capacitor in bumpless build-up layer (BBUL) technology for chipset and non-CPU applications. Benefits include improved placement, reduced inductance, and improved capacitance of bypassing capacitors and processors, and an improved method for meeting multiple-voltage requirements of a chipset or non-CPU I/O power delivery system.

Background

              As frequencies and edge rates of high performance microprocessor products increase, decoupling capacitors play more and more of an important role in reducing the system noise and suppressing the unwanted radiation. To effectively reduce the system noise, the inductance of a decoupling capacitor needs to be low.

              Bypassing capacitors are conventionally placed on the front side of a package, on the backside of a package directly underneath the die, and embedded in a package substrate. A capacitor mounted on a package is called a die-side capacitor (DSC). A capacitor mounted on the back of a package is called a land-side capacitor (LSC). 

General description

              The disclosed method includes a capacitor that is partitioned into several pieces and fabricated inside BBUL to provide power decoupling to an I/O power delivery system with multiple voltage requirements for either chipset or non-CPU applications. The partitioned capacitor can easily provide nF range capacitance. I/O power decoupling solutions for chipset and non-CPU applications typically require decoupling capacitors in nF range.

              The key elements of the disclosed method include:

·        BBUL

·        A multi-layer capacitor with checkerboard polarities is connected to power/ground (P/G) vias under a chip. The capacitor provides a good power decoupling solution due to extremely low inductan...