Browse Prior Art Database

SELF LOADING SERIAL N BIT REGISTER

IP.com Disclosure Number: IPCOM000005662D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2001-Oct-24
Document File: 2 page(s) / 76K

Publishing Venue

Motorola

Related People

Barry W. Herold: AUTHOR

Abstract

Abstract: Described herein is a unique architecture for a shift register such that the loading requires a minimal device count and the speed of operation is greatly increased over the more common architectures.

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MOTOROLA Technical Developments Volume 7 October 1987

SELF LOADING SERIAL N BIT REGISTER

by Barry W. Herold

Abstract: Described herein is a unique architecture for a shift register such that the loading requires a minimal device count and the speed of operation is greatly increased over the more common architectures.

   In the previous technology, an N bit shift register would be accompanied by a X bit counter and a count PLA, as shown in Figure 1. In this system, the LOAD signal resets the counter which forces the HOLD signal low and allows operation of the shift register and counter using the CLK signal. During operation, data is cap- tured by the shift register from the DATA signal, and the counter is incremented. When the counter reaches the count of N, the count PLA applies a high on the HOLD signal which blocks the CLK signal and stops the operation of the circuit. The speed of operation of the circuit is limited by the signal flow from the CLK through the OR gate, the X bit counter, the counted PLA and back to the OR gate. Thus, the circuit is costly in both areas of implementation and speed of operation.

   To circumvent these problems, a new architecture is recommended for situations where the shift register can be cleared prior to loading. The architecture in Figure II consists of the same N bit shift register, with the exception that the first bit is a set type flip-flop and the following N-l bits are reset type flip-flops, followed by a single reset typ...