Browse Prior Art Database

PLA MINIMIZATION VIA SELECTIVE OUTPUT INVERSION

IP.com Disclosure Number: IPCOM000005664D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2001-Oct-24
Document File: 1 page(s) / 53K

Publishing Venue

Motorola

Related People

Bill Moyer: AUTHOR

Abstract

Typical 32.bit microprocessors include the capability to detect illegal opcode combinations and force an exception to be taken if an attempt is made to execute an illegal instruction. In addition, service requests by external coprocessors presented to the main processor in the form of a coprocessor primitive are checked to determine the validity of the primitive encoding.

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Technical Developments Volume 7 October 1987

PLA MINIMIZATION VIA SELECTIVE OUTPUT INVERSION

by Bill Moyer

   Typical 32.bit microprocessors include the capability to detect illegal opcode combinations and force an exception to be taken if an attempt is made to execute an illegal instruction. In addition, service requests by external coprocessors presented to the main processor in the form of a coprocessor primitive are checked to determine the validity of the primitive encoding.

   To minimize the logic necessary to detect illegal opcodes, a PLA decoder is used. One or more class decoders may be coupled with a PLA. By selectively inverting one or more outputs of the PLA based on the output of the class decoder, the default output of the PLA when no product term decodes may be altered. These default outputs can be used to indicate illegal conditions for each class of decodes. For example, illegal in- structions in the MC68020 are detected by decoding all legal instructions, and looking for the default output of the instruction decode PLA (all ones) to indicate an illegal instruction decode. The MC68030 uses this scheme, and expands on it by providing selective output inversion in the coprocessor PLA to detect protocol violations when dealing with an external coprocessor (class l), and to detect F-line exceptions when dealing with an in- ternal coprocessor (class 2). F-line exceptions and protocol violations require different outputs from the PLA to vector the...