Browse Prior Art Database

PIN GRID ARRAY FOR HIGH-RELIABILITY CHIP CARRIER

IP.com Disclosure Number: IPCOM000005666D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2001-Oct-24
Document File: 1 page(s) / 41K

Publishing Venue

Motorola

Related People

Scott Jenkins: AUTHOR

Abstract

Pin grid arrays have been excluded from use in high-reliability chip carriers because of the difficulties in the inspection of solder joints between the chip carrier and its companion printed wiring board (FWB).

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MOZOROLA Technical Developments Volume 7 October 1987

PIN GRID ARRAY FOR HIGH-RELIABILITY CHIP CARRIER

by Scott Jenkins

Pin grid arrays have been excluded from use in high-reliability chip carriers because of the difficulties in the inspection of solder joints between the chip carrier and its companion printed wiring board (FWB).

   By limiting the plating depth of PWB thru-holes and by selective, partial plating of the grid pins, the areas of solder flow and/or wicking may be precisely controlled and the probability of solder bridging diminished (see the figure). The result is the virtual elimination of exposed solder joints in the chip carrier/FWB interface.

By essentially eliminating the basis for this inspection. the use of oin grid arrays in "high-rel" flight systems may now be seriously considered.

STANDARD CONl-IIICTlVF PATERNS

I/O PATH

NON-WICKING

SELECTIVE 7

PLATING

Y-71 iilk-! ii-

PWB

UMITED

DEPTH PLATING

SOLDERING PROFILE

0 Motorola, Inc. 1987 44

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