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A FUSE PROGRAMMABLE COLUMN REDUNDANCY FOR A BYTE-WIDE SRAM

IP.com Disclosure Number: IPCOM000005673D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2001-Oct-25
Document File: 2 page(s) / 93K

Publishing Venue

Motorola

Related People

Karl Wang: AUTHOR [+3]

Abstract

State-of-the-art, high density CMOS SRAM's generally require a divided word line architecture to simul- taneously meet performance and power consumption specifications. Because of the size of these devices, a redundancy scheme is usually employed to enhance yields. However because of the extensive data bussing associated with eight outputs, column redundancy on byte-wide static RAM's with divided word lines has proven to be complicated and costly in terms of die area. The column redundancy scheme described below is unique in that it is simple to implement, causes no access time penalty, has a high ratioof redundant columns to possible defective columns, and consumes little die area.

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MOlVROLA Technical Developments Volume 7 October 1987

A FUSE PROGRAMMABLE COLUMN REDUNDANCY FOR A BYTE-WIDE SRAM

by Karl Wang, Mark Bader, and Tim Egging

INTRODUCTION:

   State-of-the-art, high density CMOS SRAM's generally require a divided word line architecture to simul- taneously meet performance and power consumption specifications. Because of the size of these devices, a redundancy scheme is usually employed to enhance yields. However because of the extensive data bussing associated with eight outputs, column redundancy on byte-wide static RAM's with divided word lines has proven to be complicated and costly in terms of die area. The column redundancy scheme described below is unique in that it is simple to implement, causes no access time penalty, has a high ratioof redundant columns to possible defective columns, and consumes little die area.

PROBLEM:

   Figure 1 shows a possible column decoding configuration for a byte-wide divided word line part. Upon receiving a given address, the signal "column" will connect bit lines (O-3) to data lines (O-3) and bit lines (4-7) to data lines (4-7). Typically bit lines (O-3) will be selected from a section of the array on the left side of the chip and bit lines (4-7) will be selected from the right side. Data lines (O-7) correspond to outputs (O-7). The problem in implementing redundancy for this situation is that adefective column in either section can belong to one of four data bits. Therefore, a redundant column must be able to transfer to any 1 of 4 data lines. The only other solution is to replace defective columns in groups of four, which is impractical due to the corre- sponding increase in die size.

SOLUTION:

   Figure 2 shows the same column decoding section with a redundancy scheme that allows...