Browse Prior Art Database

DOUBLE LAYER POLY FOR EPROM INTERCONNECT

IP.com Disclosure Number: IPCOM000005674D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2001-Oct-25
Document File: 2 page(s) / 97K

Publishing Venue

Motorola

Related People

B. Morton: AUTHOR

Abstract

Minimization of interconnect resistance is critically important in the layout of integrated circuitry in general and EPROM devices in particular. In most MOS processes there is a single layer of polysilicon which may be used as interconnect whereverthe poly resistivity is tolerable. EPROM devicesconventionally contain two poly layers, but operate in such a way as to permit only one of them to be used as interconnect, thereby imposing the same interconnect constraints as in conventional single poly processes. A new EPROM process (see ref- erence) presents the possibility of using both layers as interconnect to produce a net resistivity substantially below that of asingle layer. The resultant reduction in interconnect resistance is enough to significantly impact performance of critical circuitry.

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MOlYlROLA Technical Developments Volume 7 October 1987

DOUBLE LAYER POLY FOR EPROM INTERCONNECT

by B. Morton

   Minimization of interconnect resistance is critically important in the layout of integrated circuitry in general and EPROM devices in particular. In most MOS processes there is a single layer of polysilicon which may be used as interconnect whereverthe poly resistivity is tolerable. EPROM devicesconventionally contain two poly layers, but operate in such a way as to permit only one of them to be used as interconnect, thereby imposing the same interconnect constraints as in conventional single poly processes. A new EPROM process (see ref- erence) presents the possibility of using both layers as interconnect to produce a net resistivity substantially below that of asingle layer. The resultant reduction in interconnect resistance is enough to significantly impact performance of critical circuitry.

Conventional EPROM processes are of two types:

Type 1 - Peripheral transistors and interconnect are built with second poly only. First poly is used in the memory array only and forms the floating gate of the memory transistors.

The first poly mask defines strips in the array which set the width of the array floating gates.

In addition to peripheral structures, the second poly mask defines floating gate transistor chan- nel lengths in the array by simultaneous etch of first and second poly.

Type 2 - Peripheral transistors as well as array transistor floating gate width are defined by the first poly mask.

The second poly mask defines no peripheral structures. It serves only to define floating gate transistor channel lengths in the memory array by simultaneous etch of first and second poly.

   In both Type 1 and Type 2 processes all double poly structures are defined by a simultaneous etch of both layers of poly. This results in a "stacked poly" structure in which first poly is not accessible to contacts because it is always covered by second poly. In aType 1 process, only first poly may be used as interconnect. In a Type 2 process, first poly may be used in t...