Browse Prior Art Database

SELF PROTECTING TRANSISTOR DESIGN

IP.com Disclosure Number: IPCOM000005679D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2001-Oct-25
Document File: 1 page(s) / 44K

Publishing Venue

Motorola

Related People

Kenneth Hutchinson: AUTHOR [+2]

Abstract

Figure 1 illustrates a self protecting transistor package 10 which includes a PTC resistor 12 interpose be- tween a semiconductor device 14 and its metal heatsinking tab 16. When the temperature of the device 14 ap- proaches its design limit, the resistance of the PTC resistor 12 increases sharply and limits the device temperature to a safe value. This approach produces very little therm0 lag between the device and the PTC resistor, and it automatically compensates for changes in the ambient temperature. The location of the PTC resistor 12, as shown, is suitable for a typical bipolar or MOS transistor as well as SCRs and triax.

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M-ROLA Technical Developments Volume 7 October 1987

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SELF PROTECTING TRANSISTOR DESIGN

by Kenneth Hutchinson and Daniel Berg

   Figure 1 illustrates a self protecting transistor package 10 which includes a PTC resistor 12 interpose be- tween a semiconductor device 14 and its metal heatsinking tab 16. When the temperature of the device 14 ap- proaches its design limit, the resistance of the PTC resistor 12 increases sharply and limits the device temperature to a safe value. This approach produces very little therm0 lag between the device and the PTC resistor, and it automatically compensates for changes in the ambient temperature. The location of the PTC resistor 12, as shown, is suitable for a typical bipolar or MOS transistor as well as SCRs and triax.

   The PTC resistorcould also be situated such that it is electrically inserted with one of tne power terminal leads of the semiconductor device. This arrangement is shown in Figure 2. Alternatively, as illustrated by the dotted lines in Figure 2, the PTC resistor could be incorporated as an internal portion of the semiconductor device. This approach produces even lesser thermal lag between the semiconductor device and the resistor than does the arrangement shown in Figure 1.

dlCONOUCTOR '997 "PC

I Ai

I ~~~~~~

CERAMIC M&L RESISTOR HEATSINK

TAB

 POWER TERMINAL 1

TEMPERATURE

CONTROL SEMICONDUCTOR TERMINAL

 POWER TERMINAL 2

0 Motorola, Inc. 1987 62

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