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A NOVEL CONTROL LOGIC FOR NON VOLATILE MEMORIES

IP.com Disclosure Number: IPCOM000005689D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2001-Oct-26
Document File: 1 page(s) / 45K

Publishing Venue

Motorola

Related People

Alain Bromm: AUTHOR

Abstract

Typically a test sequence of memories includes the programming of patterns like for example a checker- board. Usually in order to reduce the programming time a bulk programming feature is added and this feature needs some control bits which are implemented in the memory control register or at any address location.

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MO7VROLA Technical Developments Volume 7 October 1987

A NOVEL CONTROL LOGIC FOR NON VOLATILE MEMORIES

by Alain Bromm

   Typically a test sequence of memories includes the programming of patterns like for example a checker- board. Usually in order to reduce the programming time a bulk programming feature is added and this feature needs some control bits which are implemented in the memory control register or at any address location.

This invention uses the latched addresses, which are not used during bulk operation, to control the bulk operation instead of using an extra register as shown in the Figure for a byte organized memory.

CPU

RoDAESS BUS ) CONTROL

LATCHED RDDRESS BUS

1

       MEMORY BYTE DRGANISED RRRRY In x "I

1 flow D&ik+_l J

   In a bit organized memory if a checker-board is written, the row selection as described above is not suffi- cient. A column selection should be added in order to select every second column-bit. In this case two more register bits would be used, but with the simplified selection only two existing latched addresses are used.

ADVANTAGES

1. The bulk operation does not use any bit of the control register.

2. It saves silicon area.

3. It does not require reserving a specific address containing any control bits like in the prior art.

4. The logic is simpler.

5. It uses existing latches instead of designing flip-flops.

0 Motorola, Inc. 1987 76

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