Browse Prior Art Database

PROCESS-TOLERANT HIGH LEVEL SHIFTER

IP.com Disclosure Number: IPCOM000005693D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2001-Oct-26
Document File: 1 page(s) / 56K

Publishing Venue

Motorola

Related People

Patrick Clement: AUTHOR

Abstract

The proposed high level shifter changes a logic signal with a voltage swing from VSS to VDD to a logic signal with a voltage swing from VSS to VCC with VCC > VDD. Its schematic is shown in FIG 1. The inputs are a logic signal Q and its inverse Qn and the outputs are the logic signals HO and its inverse HQn. This level shifter uses CMOS devices. It has the following particularities: - no static consumption - highly process-tolerant - protected against impact-ionisation.

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MOlVROLA Technical Developments Volume 7 October 1987

PROCESS-TOLERANT HIGH LEVEL SHIFTER

by Patrick Clement

   The proposed high level shifter changes a logic signal with a voltage swing from VSS to VDD to a logic signal with a voltage swing from VSS to VCC with VCC > VDD. Its schematic is shown in FIG 1. The inputs are a logic signal Q and its inverse Qn and the outputs are the logic signals HO and its inverse HQn. This level shifter uses CMOS devices. It has the following particularities:

- no static consumption - highly process-tolerant - protected against impact-ionisation.

   The main advantage consists in being process-tolerant. This allows the circuit to work at a few MHz even with minimum size devices and large spread of technological parameters, thus compensating the fact that 6 p-channel and 10 n-channel MOS transistors are required. The n-channel MOST's N3, NS, N7 and NlO are used to protect the circuit against impact-ionisation. If no such protection is required they may be omitted.

   0 high and On low produces HQ high and HQn low because P4, N5 and N4 are switched on whilst P2, P3 and N6 are switched off. N3, N5, N7 and NlO are switched on all the time whatever the state of 0 and Qn is. There is no static consumption through Pl, N2, N3 and Nl and through path P6-NiO-N9-N6 because Nl and N9 are off respectively. At the next transition of Q and Qn, i.e. when Q becomes low and Qn high, Nl is switched on. Thus a large current flows through the path Pl-N3-N2...