Browse Prior Art Database

A MIXED TECHNOLOGY GATE ARRAY WITH ECL AND BIMOS LOGIC ON A SINGLE CHIP

IP.com Disclosure Number: IPCOM000005695D
Original Publication Date: 1988-Oct-01
Included in the Prior Art Database: 2001-Oct-26
Document File: 1 page(s) / 61K

Publishing Venue

Motorola

Related People

Kevin Deierling: AUTHOR [+4]

Abstract

A gate array design enhances the output drive of the internal logic while maintaining zero DC powerdissipa- tion and achieves unique input/output flexibility by providing inter-facing to CMOS, TTL and ECL levels. The usable system performance is limited normally by the worst case flip-flop toggle frequency which is in the range of 150-200 MHZ depending on operating conditions.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 54% of the total text.

Page 1 of 1

0 M

MOTOROLA Technical Developments Volume 8 October 1988

A MIXED TECHNOLOGY GATE ARRAY WITH ECL AND BIMOS LOGIC ON A SINGLE CHIP

by Kevin Deierling, Frank Ormerod, Nicolas Salamina and Douglas W. Schucker

   A gate array design enhances the output drive of the internal logic while maintaining zero DC powerdissipa- tion and achieves unique input/output flexibility by providing inter-facing to CMOS, TTL and ECL levels. The usable system performance is limited normally by the worst case flip-flop toggle frequency which is in the range of 150-200 MHZ depending on operating conditions.

   The internal logic of the gate array comprises a BIMOS gate section, an ECL internal cell section and a translator section to interface between the gate and cell sections. Flip-flop toggle frequencies in the ECL sec- tion of 500 MHZ are achieved with differential operation.

   Three rows of ECL internal cells each containing 15 major cells providing 990 equivalent gates. One hun- dred percent routability is ensured by providing 21 first layer metal channels between cell rows and 40 free second layer metal channels over the major cells.

   All signal interface between the BIMOS and ECL logic sections is via 37 translators which perform no logic function but can be configured as either a BIMOS-ECLor ECL-BIMOS interface. Eight reference generators provide two reference voltages and a current source voltage for the translators and major cells. Power and reference voltages are bussed vertically on t...