Browse Prior Art Database

RADIATION HARDENING TECHNIQUE

IP.com Disclosure Number: IPCOM000005702D
Original Publication Date: 1988-Oct-01
Included in the Prior Art Database: 2001-Oct-29
Document File: 2 page(s) / 86K

Publishing Venue

Motorola

Related People

Dean P Frazier: AUTHOR

Abstract

A method for radiation hardening semiconductor devices has been devised. A heavy P+. doping in the field region will improve the radiation hardening of a MOS device by preventing inversion. However, a light P doping is provided near the source/drain of a device to prevent a degradation of the breakdown voltage. The new method proposed will improve the radiation hardening of the device, without degrading the breakdown voltage.

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MOlOROLA Technical Developments Volume a October 1988

RADIATION HARDENING TECHNIQUE

by Dean P Frazier

BACKGROUND:

   A method for radiation hardening semiconductor devices has been devised. A heavy P+. doping in the field region will improve the radiation hardening of a MOS device by preventing inversion. However, a light P doping is provided near the source/drain of a device to prevent a degradation of the breakdown voltage. The new method proposed will improve the radiation hardening of the device, without degrading the breakdown voltage.

PROCESS:

   Referring to FIG. IA, a thin oxide layer 12, a silicon nitride layer 14, and a thick oxide layer 20 are,applied to a silicon substrate 10. Thick oxide 20 and nitride 14 are patterned using standard photolithography techni- ques. Next, a resist layer 26 is patterned and etched leaving an opening over a field region 25. A low dose of a dopant 28 is implanted into field region 25.

Referring to FIG. lB, resist layer 26 is removed and dopant 28 is driven-in. Another resist layer 30 is ap- plied, and patterned. Subsequently, a high dose of dopant 32 is implanted deep into field region 25.

   FIG. 1C illustrates the structure of FIG. 1B with resist layer 30, oxide layer 20, and the portion of oxide layer 12 not under silicon nitride layer 14 removed. Next, a field oxide layer 34 is grown. Silicon nitride layer 14 acts as a mask to prevent the growth of oxide in an active area 2%

   FIG. ID illustrates a completed device. Silicon...