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TESTING TEMPERATURE LIMIT CIRCUITS AT ROOM TEMPERATURE

IP.com Disclosure Number: IPCOM000005704D
Original Publication Date: 1988-Oct-01
Included in the Prior Art Database: 2001-Oct-29
Document File: 3 page(s) / 133K

Publishing Venue

Motorola

Related People

Bill Dunn: AUTHOR

Abstract

One of the design aims with SMARTMOS devices is adequate testability of the final encapsulated device. A typical device has an input lead to drive the power output device, two diagnostic leads for interrogation of the functionality of the device, and a load condition lead. Also a fault or status pin is provided to inform the controllingmediumof thestatusof theoutput(figure l).TheinputsareTTLcompatible,and theoutput iscapable of controlling several amps.

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MOTOROLA Technical Developments Volume 8 October 1988

TESTING TEMPERATURE LIMIT CIRCUITS AT ROOM TEMPERATURE

by Bill Dunn

   One of the design aims with SMARTMOS devices is adequate testability of the final encapsulated device. A typical device has an input lead to drive the power output device, two diagnostic leads for interrogation of the functionality of the device, and a load condition lead. Also a fault or status pin is provided to inform the controllingmediumof thestatusof theoutput(figure l).TheinputsareTTLcompatible,and theoutput iscapable of controlling several amps.

   In wafer form, several internal nodes can be checked or tested at probe for functionality. In the packaged part, however, only the leads shown in figure 1 are available for testing. As a result, the full functionality of a packaged device can not always be fully checked easily and directly.

   One method to circumnavigate this problem is to design in a test mode For example, TTL inputs are typically subjected to a maximum input voltage of 5.5 volts under normal operating conditions; but, if one of the inputs were taken to 12 volts, a test latch and hence a test mode can be activated. Under this condition the other in- puts can now be used for test functions instead of normal control functions.

   This test mode can be used to exercise such functions as the TLIM (temperature limit) function at room temperature. TLIM is used to protect the power device at elevated temperatures due to excessive internal power dissipation which could occur under fault conditions. The TLIM normally operates in the region of 160 degrees Celsius and testing the device would require its temperature being elevated beyond 160 degrees Celsius. This would be an extremely difficult and expensive task given the available test equipment.

   Figures 2 and 3 show two circuits that are used for temperature sensing. In the circuit of figure 2, a fixed current from a current regulator is sourced through P- channel transistor PI. This current is mirrored in tran- sistors R, R, and P,, which in turn pass a current II through a resistor R, sets up a small hysteresis current I,, and provides the load current for the NPN transistor Q4.

   The value of R, is chosen so that the hRI voltage drop is equal to the base-emitter voltage, VBE, of Q, at the required elevated trip temperature. At room temperature the voltage across R* is less than the VBE of Q, so that Q? is off and its collector voltage is approximately equal to the supply voltage. As the temperature of the circuit increases, the VsE of Q? decreases at a rate of 2mVI degree Celsius. When the VeE of Q, reaches the voltage across RI (the temperature trip point), Q? turns on and its collector goes low to activate the TLIM output.

   Also shown in figure 2 is a test circuit that allows the temperature limit circuit to be exercised at room t...