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FLOATING POINT PIPELINE PARTITIONING

IP.com Disclosure Number: IPCOM000005710D
Original Publication Date: 1988-Oct-01
Included in the Prior Art Database: 2001-Oct-30
Document File: 3 page(s) / 184K

Publishing Venue

Motorola

Related People

Yoav Talgam: AUTHOR [+4]

Abstract

The M78000 floating point unit consists of two physical pipelines, a five stage add pipeline and asix stage multiplier pipeline, which have logically shared first and last stages. The add pipeline executes single and dou- ble precision floating point add, subtract, compare, divide instructions as well as floating point conversion to integer, integer conversion to floating point, and unsign integer divide instructions. The multiply pipeline ex- ecutes single and double precision floating point multiply and integer multiply instructions. The stages in each pipeline were balanced to assure approximately equivalent timing delays through each stage so that technology improvements will result in a uniform speed improvement throughout the pipelines. Tradeoffs of performance versus area were made where necessary to allow the floating point unit to be combined with the integer unit on a single chip.

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MOTOROLA Technical Developments Volume 8 October 1988

FLOATING POINT PIPELINE PARTITIONING

by Yoav Talgam, Mitchell Alsup, Marvin Denman and Janet Sooth

   The M78000 floating point unit consists of two physical pipelines, a five stage add pipeline and asix stage multiplier pipeline, which have logically shared first and last stages. The add pipeline executes single and dou- ble precision floating point add, subtract, compare, divide instructions as well as floating point conversion to integer, integer conversion to floating point, and unsign integer divide instructions. The multiply pipeline ex- ecutes single and double precision floating point multiply and integer multiply instructions. The stages in each pipeline were balanced to assure approximately equivalent timing delays through each stage so that technology improvements will result in a uniform speed improvement throughout the pipelines. Tradeoffs of performance versus area were made where necessary to allow the floating point unit to be combined with the integer unit on a single chip.

   The first and last stage of each pipeline are shared so that the floating point unit represents a special function unit and adheres to the special function unit interface protocol. This simplifies the control along the core-fpu interface and allows the floating point instruction decode, precise exception logic, imprecise excep- tion logic, control registers, and writeback arbitration logic to be shared. Stage 0 of each pipeline is physically shared for the instruction decode, exception detection logic, exponent pipeline, and the core-fpu handshake logic. The stage 0 data path is logically shared (either an addpipe or a multpipe instruction can occupy it at one time) but is physically separate. Both the add and multiply pipelines output a53 bit data bus from the stage 0 latches with the most significant bit for single precision, double precison, and integer operands aligned to one bit position below the hidden bit. The low order bits for singles and integers are filled with zeros. Stage 0 of the exponent pipeline converts the incoming single or double precision exponent into a twelve bit quantity by inverting the highest order bit and sign extending to fill the remaining high order bits. The twelve bit expo. nent adderlsubtractor determines the exponent difference for add, subtract, divide, comparison, and conver- sion operations or the exponent sum for multiplications. The exponent stage 1 master latches are also shared in order to improve the timing on the detection of floating point busy and to reduce silicon area. Logically stage 1 master of the data path is also logically shared but physically separate. From this point, stages 1, 2,3, and 4 of the addpipe and stages 1,2,3,4,5 of the multpipe are separate both physically and logically. The pipeline stages advance on the rising edge of phil (the master clock) if the next stage is not busy.

   Stage 1 master latches of the multpipe determine...