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Browse Prior Art Database

RESULT WRITE BACK ARBITRATION SCHEME OF THE MC88100

IP.com Disclosure Number: IPCOM000005713D
Original Publication Date: 1988-Oct-01
Included in the Prior Art Database: 2001-Oct-30
Document File: 1 page(s) / 76K

Publishing Venue

Motorola

Related People

Mitchell Alsup: AUTHOR [+3]

Abstract

The MC88100 is a highly pipelined microprocessor with multiple functional units. The pipelines of these functional units are often of varying and even variable lengths. The register file is only capable of handling one result per clock. This brings about the requirement that the write back slot must be arbitrated for in each clock to allow efficient instruction execution and pipelining.

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MOTOROLA Technical Developments Volume 8 October 1988

RESULT WRITE BACK ARBITRATION SCHEME OF THE MC88100

by Mitchell Alsup, William Lau and Marvin Denman

   The MC88100 is a highly pipelined microprocessor with multiple functional units. The pipelines of these functional units are often of varying and even variable lengths. The register file is only capable of handling one result per clock. This brings about the requirement that the write back slot must be arbitrated for in each clock to allow efficient instruction execution and pipelining.

   The MC88100 design gives the highest priority to single cycle instructions. When a single cycle instruc- tion is issued that requires writing back a result into the register file, the write back slot is automatically re- served. A store operation also effectively reserves a write back slot due to the implementation. The register file is implemented using three ports. Two ports are outputs and supply the source operands. The third port is bidirectional and is used for both write backs and store data. The sharing of this port prevents its arbitration during a store operation.

   The second priority is given to special function unit (SFU) instructions. An SFU will be granted a write back slot when a single cycle instruction does not need the write back slot for any reason. The architecture supports multiple special function units, but for the purpose of write back arbitration all of the special function units can only request a single write back during each clock. Arbitration between different SFUs should be done outside of the normal write back arbitration mechanism. For example in the MC88100 the floating point unit is implemented logically as one SFU but physically as two SFUs. Within the floating point unit the two physical units arbitrate for the right to write back from the logical SFU. The logical SFU then arbitrates for a write back slot into the regis...