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A Method for Modulating the Gate Coupling in Split Gate Flash Memory Devices

IP.com Disclosure Number: IPCOM000005723D
Original Publication Date: 2001-Oct-30
Included in the Prior Art Database: 2001-Oct-30
Document File: 4 page(s) / 112K

Publishing Venue

Motorola

Related People

Alexander Hoefler: AUTHOR [+2]

Abstract

In a Split Gate Flash (SGF) electrically erasable programmable read only memory (EEPROM) technology, it is occasionally necessary to adjust the gate coupling ratio of the bitcell in order to optimize device performance or retarget device specifications after process or design changes. In this paper, we describe a method that allows a gate coupling ratio adjustment by taking advantage of the fact that the gate coupling ratio in SGF devices is determined by the thickness of the dielectric layer(s) located in the gap between floating gate and control gate. In certain implementations, there is a small silicon nitride spacer placed in this gap. The method presented in this paper proposes to change the thickness and/or dielectric properties of this small spacer deliberately, in order to modulate the thickness of the dielectric between the control gate and the floating gate, and thus the gate coupling ratio. The method can be useful for purposes such as adjustment of read currents or electric fields for program and/or erase performance, independently of other dielectric layers. The method can also improve the scalability of a bitcell in a split gate flash technology.

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A Method for Modulating the Gate Coupling in Split Gate Flash Memory Devices

Alexander Hoefler, Nina Telang

Abstract

In a Split Gate Flash (SGF) electrically erasable programmable read only memory (EEPROM) technology, it is occasionally necessary to adjust the gate coupling ratio of the bitcell in order to optimize device performance or retarget device specifications after process or design changes. In this paper, we describe a method that allows a gate coupling ratio adjustment by taking advantage of the fact that the gate coupling ratio in SGF devices is determined by the thickness of the dielectric layer(s) located in the gap between floating gate and control gate. In certain implementations, there is a small silicon nitride spacer placed in this gap. The method presented in this paper proposes to change the thickness and/or dielectric properties of this small spacer deliberately, in order to modulate the thickness of the dielectric between the control gate and the floating gate, and thus the gate coupling ratio. The method can be useful for purposes such as adjustment of read currents or electric fields for program and/or erase performance, independently of other dielectric layers. The method can also improve the scalability of a bitcell in a split gate flash technology.

Body

A conventional split gate flash memory cell [1] is shown in Figure 1 A.). The main elements of the conventional cell are the floating gate (usually, but not necessarily, made of polysilicon), control gate (usually, but not necessarily, made of polysilicon), coupling dielectric (usually, but not necessarily, made of silicon dioxide), and interpoly dielectric (usually, but not necessarily, made of a combination of a silicon nitride spacer and silicon dioxide layers).

It is desirable to adjust the gate coupling ratio of the bitcell (defined as the ratio of the capacitance between floating gate and control gate, to the total floating gate capacitance) for the following reasons:

·        Change of the read current/control gate voltage requirements.

·        Change of the thickness requirements of coupling dielectric (or coupling oxide).

·        Optimization of program disturb or read disturb (i.e. situations where program or read biases are applied to the bitcell, except for the control gate which is biased such that the cell is unselected).

·        Scaling down of the flash cell area while keeping the coupling dielectric at the same thickness. A shorter gate length of the cell (with a shorter floating gate) will have an increased gate coupling, since the coupling oxide thickness cannot be scaled without compromising data retention behavior.

The problem of the standard device is that the gate coupling ratio cannot be changed without changing other fundamental device characteristics.

One feature in the standard device is the narrow spacer located a...