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An Image Processing System Employing Network Processors

IP.com Disclosure Number: IPCOM000005725D
Publication Date: 2001-Oct-31
Document File: 5 page(s) / 199K

Publishing Venue

The IP.com Prior Art Database

Related People

Amir NOY: INVENTOR [+2]

Abstract

An inspection system includes image acquisition means acquiring an image of an article to be inspected and packaging the image into stream of image packets, each of which corresponds to a portion of the image. A required image processing step may be indicated in the packet. The image packets are distributed to an available processor, in an array of processors, operative to perform a desired image processing operation on the image packet and to forward a modified image packet to another destination. At the new destination a modified image packet is either further modified and forwarded to another processing destination, or is combined with other modified image packets and then further processed to detect defects.

This text was extracted from a Microsoft Word document.
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AN IMAGE PROCESSING SYSTEM
EMPLOYING NETWORK PROCESSORS

BACKGROUND OF THE INVENTION

1.      Network processors are the newest generation of processors used network communications.  Their tasks include routing/switching management inside standard routers and switches.

2.      Conventional routing and switching management systems perform four basic tasks:

a. Data packet analyzing & parsing;

b. Searching lookup tables for destination addresses and pre-defined routing rules;

c. Resolving destinations and rules for routing; and

d. Modifying data packets as necessary.

3.      History – Initially, router/switch manufacturers used standard “general purpose” processors that were flexible, easily programmable, and could handle low data rates as needed. Later Asics were employed in order to handle rapidly increasing data rates. The third generation, namely network processors, has now come into existence.  Network processors are able to handle both high data rates (today up to 10 Gb/s) and are able to manage complicated and flexible data transfer policies including policy based networking (for example routing based on quality of service), usage based accounting, server load balancing and other complex networking tasks.

4.      Third generation network processors are available from various suppliers, including Lucent, Nortel, Alcatel, Motorola, Intel and IBM.

5.      There are several basic architectural structures for network processors, however they all share the same basic elements:

  • High data rate I/O,
  • Some simple parallel processors (RISC processors for example, with limited instruction set); and
  • High data rate connection to memory (both DRAM and SRAM) for accessing lookup tables.

6.      There are two main strategies for implementing the network processors –

a.       Building custom boards around such a processor or

b.      (Preferred) using standard switches with only custom software.

Image processing tasks

1.      The image processing tasks are divided into two main classes - simple global algorithms that are performed on large portions of a data stream, and more complicated localized algorithms that are performed only on small sub images, which are extracted from the data stream by application of the global algorithms.

2.      Typically, at least some algorithms involve image analysis by comparison between data from an object being inspected and reference data typically derived from CAM (computer aided manufacturing) data or “golden image ” data which is obtained from an inspection of an article which is known to be non-defective.

3.      Conventionally, the relatively simple global algorithms are implemented in custom hardware, for example FPGAs (field programmable gate arrays), while the more complicated localized algorithms are performed in general computer stations which may be in the form of a single very powerful computer or a cluster of simple computers.

4.      Typically, the simple algorithms include small defect detection by analysis of gray level images, generation of a binary representation of an...