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IMPROVED MATCHED RESISTOR MANUFACTURE

IP.com Disclosure Number: IPCOM000005732D
Original Publication Date: 1988-Oct-01
Included in the Prior Art Database: 2001-Oct-31
Document File: 1 page(s) / 65K

Publishing Venue

Motorola

Related People

Dervin L. Flowers: AUTHOR [+2]

Abstract

In many cases integrated circuit devices require a pair of resistors, matched as closely as possible in value to meet the requirements of the circuit. This has frequently been attempted using doped polysilicon which is later photolithographically patterned to form the resistor structures of the appropriate physical geometry. The yield of pairs matched to the device requirements is often significantly less than 100% resulting in severe device yield losses. The goal of this study was to have resistor pairs matched to within one percent and overall have resistor values, chip to chip and wafer to wafer match within ten percent for the circuit to operate.

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MOTOROLA Technical Developments Volume 8 October 1988

IMPROVED MATCHED RESISTOR MANUFACTURE

by Dervin L. Flowers and Carl D'Acosta

   In many cases integrated circuit devices require a pair of resistors, matched as closely as possible in value to meet the requirements of the circuit. This has frequently been attempted using doped polysilicon which is later photolithographically patterned to form the resistor structures of the appropriate physical geometry. The yield of pairs matched to the device requirements is often significantly less than 100% resulting in severe device yield losses. The goal of this study was to have resistor pairs matched to within one percent and overall have resistor values, chip to chip and wafer to wafer match within ten percent for the circuit to operate.

   In the work described here both the problem and the solution are illustrated. Devices were made and polysilicon was deposited and doped with boron which was activated in nitrogen at 900X for 20 minutes. The polysilicon resistors were then photolighographically defined. Next, 750A of pyrolytic oxide (TEOS) was deposited. Then half of the wafers with either Bll or BF2 implants (7.8E14 at 40KeU) were deposited with 1250A of silicon nitride. Preohmic patterns were cut in the dielectric and Al metallization was defined for the contact pattern. Sheet resistance after final processing was 1145+15 ohms per square for the Bll implanted chips and 1642?39 ohms per square for the BF2 implanted ma...