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IMPROVED PLL LOCK TIME BY PREDICTIVE PROGRAMMING

IP.com Disclosure Number: IPCOM000005740D
Original Publication Date: 1988-Oct-01
Included in the Prior Art Database: 2001-Nov-01
Document File: 3 page(s) / 124K

Publishing Venue

Motorola

Related People

William J. Ooms: AUTHOR [+2]

Abstract

The lock time of a simple phase locked loop shown in figure 1 below may be improved by changing the loop divider value while changing frequencies. When a tri-state charge pump phase detector is used, optimum lock time will be achieved if the output current can be kept at a maximum constant output for enough time to provide sufficient charge to bring the loop filter capacitors to the desired final state. This can be accom- plished as shown in the timing diagram shown in figure 2.

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Page 1 of 3

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MOTOROLA Technical Developments Volume 8 October 1988

IMPROVED PLL LOCK TIME BY PREDICTIVE PROGRAMMING

by William J. Ooms and James S. Irwin

   The lock time of a simple phase locked loop shown in figure 1 below may be improved by changing the loop divider value while changing frequencies. When a tri-state charge pump phase detector is used, optimum lock time will be achieved if the output current can be kept at a maximum constant output for enough time to provide sufficient charge to bring the loop filter capacitors to the desired final state. This can be accom- plished as shown in the timing diagram shown in figure 2.

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FIG. 2

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   In this example, the loop is initially locked at some old frequency corresponding to a loop divider value of 35. At this time, a new number is put into the loop divider which is larger than the normal value for the new frequency. This gives a constant maximum current pulse out of the phase detector for some length of time which is determined by the loop divider value. This value has been chosen to give a current pulse which is just enough to charge both capacitors in the loop filter to a voltage corresponding to the desired new frequen- cy. However, the phase of the loop divider output and the reference input are not the same at this point. To achieve zero phase between the loop divider and reference, a new number is loaded into the loop divider for a short period of time (a value of 6 in the example) to restore the phase detector inputs to the same phase.

   In this example, there are two capacitors in the phase detector. Although the total charge in the capacitors might be correct at this point in time, the charge is not correctly distributed. It may take several cycles for the charge to re-distribute properly. During this time, the inputs to the phase detector must be kept at zero phase difference to prevent any additional charge contribution. This means that the number in the loop divider must be adjusted for perhaps a few cycles. In the example shown, the loop divider is set to 47 for one cycle before going to its final steady state value of 40.

0 Motorola, Inc. 1986 70

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MOlOROlA Technical Developments Volume 8 October 1988

   A further improvement may be realized by using a multiple output phase detector as shown in figure 3 below. A second tri-state charge pump output is added to the phase detector and is connected to the 2nd capacitor...