Browse Prior Art Database

MOS DIFFERENTIAL COMPARATORS WITH INTERNAL HYSTERESIS

IP.com Disclosure Number: IPCOM000005745D
Original Publication Date: 1988-Oct-01
Included in the Prior Art Database: 2001-Nov-01
Document File: 3 page(s) / 115K

Publishing Venue

Motorola

Related People

Jules Campbell: AUTHOR

Abstract

The advancements of MOS Integrated Circuit technology have led to higher levels of system integration on silicon. Open loop differential amplifier circuits are frequently used as comparators to interface analog signals to digital processing circuits in applications such as the detection of transition edges, voltage levels, etc. Hysteresis in the switching threshold, as shown in Fig 1, is desirable to reduce the instability of the comparator output when the input signal level is near the comparator threshold and electrical noise is present in the system.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 50% of the total text.

Page 1 of 3

0 M

MOTOROLA Technical Developments Volume a October 1986

MOS DIFFERENTIAL COMPARATORS WITH INTERNAL HYSTERESIS

by Jules Campbell

   The advancements of MOS Integrated Circuit technology have led to higher levels of system integration on silicon. Open loop differential amplifier circuits are frequently used as comparators to interface analog signals to digital processing circuits in applications such as the detection of transition edges, voltage levels, etc. Hysteresis in the switching threshold, as shown in Fig 1, is desirable to reduce the instability of the comparator output when the input signal level is near the comparator threshold and electrical noise is present in the system.

   Many methods exist for the introduction of hysteresis. The most common technique employs positive feed- back from the comparator output, thereby shifting the reference voltage. In this case, the amount of hysteresis is usually proportional to the comparator output swing, which is proportional to the supply voltage.

   The offset voltage of a MOS differential stage depends on careful matching of: (1) threshold voltages, which vary with process and temperature; (2) current density, which depends on device size and bias level; (3) layout symmetry; (4) photo-lithographic variation and defects; and (5) the design of the subsequent amplifier stage. Most MOS gain circuits operate in the "square-law': or saturation region, where drain current is approximately:

Ids =k'(W/L)(Vgs - Vt)"2 (1)

Equation one can be manipulated and applied to solve for the offset voltage of a differential pair:

vos = vgs1 - vgs2

= (Idsl/(k'(Wl/Ll)))"0.5 - (Ids2/(k'(WZL2)))"0.5 + DeltaVt,

where:

DeltaVt = Vtl - Vt2,

which is assumed to be negligible.

(4)

   Two techniques have been developed to exploit the use of current density mismatch in order to deliberate- ly introduce an offset voltage into the differential stage as a means of providing hysteresis. The hysteresis can be implemented by either a continuous or sampled feedback method. Practical values for the magnitude of the hysteresis range from tens to hundreds of millivolts. However, it should be noted that the techniques presented do not offer precision control of the magnitude of the hysteresis.

   The first technique, shown in Fig. 2, employs a deliberate device geometry mismatch by switching on a transistor in parallel to one transistor of the differential pair. Note that the dif...