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SYNCHRONIZATION METHOD FOR DUAL ASYNCHRONOUS TIMERS

IP.com Disclosure Number: IPCOM000005757D
Original Publication Date: 1988-Oct-01
Included in the Prior Art Database: 2001-Nov-02
Document File: 2 page(s) / 125K

Publishing Venue

Motorola

Related People

Joan DeLuca: AUTHOR [+3]

Abstract

Today's pagers require extended battery life to remain competitive in the marketplace. One way to accomplish this is to operate the pager's microcomputer at a higher speed fordecoding and at a lower speed while battery saving. Operating the microcomputer at a lower speed can greatly reduce the operating current. The use of a frequency synthesizer to modify the input clock frequency to the microcomputer can accomplish the desired speed changes.

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MOTOROLA Technical Developments October 1988

SYNCHRONIZATION METHOD FOR DUAL ASYNCHRONOUS TIMERS

by Joan DeLuca, Mike DeLuca and Mario Rivas

   Today's pagers require extended battery life to remain competitive in the marketplace. One way to accomplish this is to operate the pager's microcomputer at a higher speed fordecoding and at a lower speed while battery saving. Operating the microcomputer at a lower speed can greatly reduce the operating current. The use of a frequency synthesizer to modify the input clock frequency to the microcomputer can accomplish the desired speed changes.

   The first time the pager begins decoding a signal, the pager must synchronize to the transmitted signal. This takes place when the microcomputer bus is operating at high speed. Once the pager is synchronized to the transmitted signal, the pager may enter a battery save interval to save current. An important constraint of a battery save interval is that the pager maintain sync to the transmitted signal while in battery save. Since a reduction in the bus speed is desired while in battery save, the risk of loosing sync is present.

   The risk can be eliminated by using a two timer system. A low speed timer operating from a crystal time base and a high speed timer operating from the synthesized bus. The low speed crystal timer consumes little current during battery saving and the high speed bus timer gives very good resolution during the bit sync (and decoding) process. Because of the synthesizer, the exact relationship between the two timers cannot be cer- tain and the two timers are effectively asynchronous.

   The use of two asynchronous timers does have special constraints. There will be a phase difference be- tween the two timers (where does one timer begin timing vs. another timer - edge to edge). This phase dif- ference is important when transferring control from one timer to another. This phase difference can cause loss of accurate real time keeping. Therefore, a method of synchronizing these two asynchronous timers is necessary. To perform this task, the phase difference between the two timers must be identified, and adjustments made when transfer between the timers take place.

   FIG. 1. shows the method for determining the phase difference between the two asynchronous timers. The phase difference is calculated just before the pager is to enter the battery save interval. The latency of the crystal timer is determined by using the high speed bus timer effectively as a stop watch. The latency is calculated and stored, control is transferred to the crystal timer for the battery save interval and timing is restored when the transfer is made from the slow crystal timer to the high speed bus timer when the pager exits battery save. FIG 2. shows the method of restoring phase difference information.

METHOD OF DETERMINING PHASE DIFFERENCE

   A system which has two asynchronous timers, one timer which derives its time base from the crystal and one which derives its t...