Browse Prior Art Database

DIGITAL VOLUME CONTROL USING DUTY CYCLE TECHNIQUE

IP.com Disclosure Number: IPCOM000005760D
Original Publication Date: 1988-Oct-01
Included in the Prior Art Database: 2001-Nov-02
Document File: 3 page(s) / 134K

Publishing Venue

Motorola

Related People

James Elton Berry: AUTHOR

Abstract

This paper shows how to use digital logic to create a completely flexible Digital Volume Control device, utilizing the Fourier characteristics of digital signals with different duty cycles. The device is particularly useful in products in which a variable tone is desired, such as a paging receiver.

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MOTOROLA Technical Developments Volume a October 1988

DIGITAL VOLUME CONTROL USING DUTY CYCLE TECHNIQUE

by James Elton Berry

   This paper shows how to use digital logic to create a completely flexible Digital Volume Control device, utilizing the Fourier characteristics of digital signals with different duty cycles. The device is particularly useful in products in which a variable tone is desired, such as a paging receiver.

   A typical tone alert circuit is shown below in Figure 1. A control input is used to turn transistor Ql on and off at some given frequency. The control input is driven by any device that can produce a continuing pulse train with variable duty cycles, such as a microcomputer I10 line or a comparator with input triangle wave and variable reference voltage (see Figure 2). An alternative to these two approaches is to take the Exclusive OR of phase delayed square waves with half the desired output frequency, in which case the output duty cycle is determined by the amounlof phase delay (see Figure 3). This can be done using the circuit of Figure 4, which is easy to implement, repeatable, and takes less die space and UC time than the above methods.

   The circuit exploits the nature of the Fourier spectrum of a square wave signal. The square wave alternates between zero and some positive value. The "up time" is defined as the time during each cycle that the function is positive (2"Tl). Duty cycle then equals [(2'Tl)/To]'lOO%, where Frequency = l/To. The a(0) coefficient represents the average value, or DC component, of each signal. For kz 0, the Fourier coefficients are defined as:

a(k)=[sin(k'Wo'Tl)]/k*Pi

and for k=l, a(l)=sin(Wo'Tl)/Pi.

The a(1) coefficients are as shown below for the specified duty cycles.

Duty Cycle (%) a(o) a(l) Rel power

Y5

0.5 0.318 0 dB
0.25 0.225 -3dB
12.5 0.125 0.1218 - 8.33 dB
6.25 0.0625 0.0621 - 14.16 dB
3.125 0.03125 0.0312 - 20.16 dB

   The power input at the fundamental frequency dominates the SPLoutput (for duty cycles < 50%) because the rolloff of the transducer occurs below the second harmonic for most commercially available transducers. Instead of lowering the transducer drive level through hardware, the SPL is attenuated by reducing the fun- damental frequency component of the input.

   Again referring to Figure 4, the number of available output levels is limited by N and the length of the shift register, which generates phase delayed signals of the fundamental. These phase delayed signals may be XOR'd with the fundamental (Sl) to produce signals of the same frequency but different duty cycles (See Figure 3). If m is the length of the shift register, the number of available duty cycles is m-l. M is limited by (N/2+1) because form> (N/2+1), (Si XOR Sm) produces aduty cycle greaterthan 50%. Since fundamental output peaks at 50% duty cycle, there is no need for these signals. The resolution in duty cycle is determined by a l/(m-1) relation- ship. The...