Browse Prior Art Database

CONSTANT VD - ID PROGRAMMING OF EPROM MEMORY CELLS

IP.com Disclosure Number: IPCOM000005767D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2001-Nov-05
Document File: 2 page(s) / 124K

Publishing Venue

Motorola

Related People

I.A. Lesk: AUTHOR [+3]

Abstract

It is customary to program an EPROM element by applying drain and control gate biases (relative to the source) such that hot electrons generated in the substrate near the Si-SiOz interface surmount the interface barrier, and drift to the floating gate in the oxide electric field. The purpose of this paper is to show that fastest programming of an EPROM with a given channel length can be accomplished by controlling the gate voltage such that drain current stays relatively constant.

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MOlVROLA Technical Developments August 1989

CONSTANT V, - lo PROGRAMMING OF EPROM MEMORY CELLS

by I.A. Lesk, SRDL, James Whitfield & Charles Varker

   It is customary to program an EPROM element by applying drain and control gate biases (relative to the source) such that hot electrons generated in the substrate near the Si-SiOz interface surmount the interface barrier, and drift to the floating gate in the oxide electric field. The purpose of this paper is to show that fastest programming of an EPROM with a given channel length can be accomplished by controlling the gate voltage such that drain current stays relatively constant.

   Figure 1 sketches an EPROM cell, which provides access to source, drain, and control gate regions. Voltage on the floating gate (V,) is determined by voltages on the control gate (V,) and drain (VO), interelectrode capacitances, and the net charge on the floating gate (Q,). A programmed EPROM cell has sufficient negative QFG to drive the (control gate) threshold voltage of the device appreciably positive. Erasing is accomplished by means of intense energetic UV. irradiation to raise floating gate electron energies above that of the Si-SiOs bar- rier, permitting them to enter the SiOz and drift away in the field set up by the charge on the floating gate. An erased EPROM cell will have a small net negative charge on the floating gate. The fact that an EPROM does not over-erase during extended U.V. exposure (that is, does not end up with a net positive charge on the floating gate to drive the cell into a depletion mode), indicates that energetic electrons are not driven into the SiOz, but merely made available for drift in an oxide electric field.

   Figure 2 sketches some equipotentials for V, <<Vr,. Drain regions are considered to be heavily doped with abrupt P-N junctions, desirable for fastest EPROM performance (but undesirable for short channel MOS tran- sistors because of excessive hot electron damage to the Si-SiOl interface). To the left of point C (e.g. at point
A), electric field in the substrate, Ea, has a vertical component in a direction to drift electrons to the Si-SiOz interface, and the vertical component of the electric field in the SiOn is in a direction to drift electrons toward the floating gate. However, Ea is small, so few hot electrons are generated in the vicinity of point A. To the right of point C, e.g. at point 6, more hot electrons are generated because electric fields in the Si are higher. However, the contribution to programming by hot electrons generated to the right of point C is minimal because com- ponents of electric fields perpendicular to the surface are in a direction to drive hot electrons away from the Si-SiOz interface and to return any hot electrons that reach the interface back to the substrate. This effect is remarkably demonstrated in the FETMOS E'...