Browse Prior Art Database

PHASE LOCK LOOP

IP.com Disclosure Number: IPCOM000005769D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2001-Nov-05
Document File: 4 page(s) / 170K

Publishing Venue

Motorola

Related People

Michael Gallup: AUTHOR [+3]

Abstract

The 68040 microprocessor utilizes a phase lock loop (PLL) in the generation of the microprocessor clocks. The PLL block controls the skew between the external system bus clock BCLK and the internal t368040 clock. The 68040 uses a quadrature set of clocks called "t" clocks. This skew control is performed with all digital cir- cuitry. The PLL block is comprised of seven logical blocks, a phase detector, clock control for the delay line and shifter, delay line, a linear up/down shifter, a clocking mode multiplexor, at clock generator, and a set/reset latch. Referring to Figure 1 the components of the PLL block are indicated. The PLL block uses two inputs from the external world, they are, the system bus clock BCLK and the processor clock PCLK. The PLL circuit uses three inputs from internal sources, the reset signal rsfpll, the test by-pass signal qbypass, and the test lock signal aflockx. The frequency relationship between the BCLK and the PCLK signals must always be a factor of two; the frequency of PCLK must be twice that of BCLK. Forthe current design goals, the frequency of PCLK is50MHz.

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m MO7VROLA Technical Developments

Volume 9 August 1989

PHASE LOCK LOOP

by Michael Gallup, Ken Scheuer, Ashok Someshwar

   The 68040 microprocessor utilizes a phase lock loop (PLL) in the generation of the microprocessor clocks. The PLL block controls the skew between the external system bus clock BCLK and the internal t368040 clock. The 68040 uses a quadrature set of clocks called "t" clocks. This skew control is performed with all digital cir- cuitry. The PLL block is comprised of seven logical blocks, a phase detector, clock control for the delay line and shifter, delay line, a linear up/down shifter, a clocking mode multiplexor, at clock generator, and a set/reset latch. Referring to Figure 1 the components of the PLL block are indicated. The PLL block uses two inputs from the external world, they are, the system bus clock BCLK and the processor clock PCLK. The PLL circuit uses three inputs from internal sources, the reset signal rsfpll, the test by-pass signal qbypass, and the test lock signal aflockx. The frequency relationship between the BCLK and the PCLK signals must always be a factor of two; the frequency of PCLK must be twice that of BCLK. Forthe current design goals, the frequency of PCLK is50MHz.

   The phase detector block is used to determine the phase between the system bus clock BCLK and the internally generated equivalent, pgbcfk (25MHz set on f3, reset on f7) signal. The output of the phase detector is an up/down indication. This up/down signal controls the tap selection on the delay line. The phase detector has a level shifting circuit on the input of the BCLK side that is used to translate the TTI level to internal levels. To keep the delays through the front end of the phase detector equal, the same circuit is placed on the pgbclk side also. In order to reduce the oscillation around the lock point (i.e. jitter) the sensitivity of the phase detector is reduced so that phase differences of about 50% to 70% of a pair delay will cause the delay line tape to be adjusted.

   The clock control block takes the up/down signals and buffers them to control the linear shifter block that selects the tap from the delay line. The clock control block has an input that in test mode will allow the blocking of the shifter clocks that move the tap on the delay line. The input signal is called of/o&x. This has the effect of locking the PLL circuit.

   The delay line is comprised of 112 inverter pairs with 112 taps from the "true" version of the pclki input signal (internal version of the PCLK input) to the delay line. The linear shifter has 112 shift elements with only one bit set in the shifter at any one time. The delay line with the shifter compromise the mechanism that con- trols the phase of the PCLK used in generating the t clocks. This is done by shifting "up" to select a tape one delay later than the current setting or shifting 'down" to select a tap one delay tap earlier than the current set- ting. This has the effect of changing th...