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TESTER ON A CHIP (TOAC) OR APPARATUS FOR APPLICATION OF TESTS FOR EMBEDDED TEST POINTS

IP.com Disclosure Number: IPCOM000005776D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2001-Nov-05
Document File: 5 page(s) / 178K

Publishing Venue

Motorola

Related People

William D. Atwell Jr.: AUTHOR [+3]

Abstract

What are the problems solved by this structure? Consider a production test suite (i.e., a collection of test vectors) for an integrated microprocessor with an asynchronous bus protocol. This test suite assumes the existence of two essential conditions: (1) certain external test points or "pins" which are directly accessible by test equipment, and (2) although it is permissible to vary the time between consecutive bus cycles, once a bus cycle is initiated, it must be executed in real-time to accomplish a satisfactory test.

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m MOTOROLA Technical Developments V

Volume 9 August 1989

TESTER ON A CHIP (TOAC) OR APPARATUS FOR APPLICATION OF TESTS FOR EMBEDDED TEST POINTS

by William D. Atwell Jr., William C. Bruce Jr., Grady L. Giles

What are the problems solved by this structure?

   Consider a production test suite (i.e., a collection of test vectors) for an integrated microprocessor with an asynchronous bus protocol. This test suite assumes the existence of two essential conditions: (1) certain external test points or "pins" which are directly accessible by test equipment, and (2) although it is permissible to vary the time between consecutive bus cycles, once a bus cycle is initiated, it must be executed in real-time to accomplish a satisfactory test.

   Suppose, at some time later, we embedded the aforementioned integrated circuit as a module in a larger design. Further suppose that it is impossible or impractical to modify the new device such that - in a test mode - the l/O pins of the embedded module can be accessed directly at the pins of the new device. If one wishes to utilize the existing production test suite to test the embedded module, there is a problem because the external pin assumption has been violated. This is the problem being addressed by this structure.

Description of the structure, including its operation, purpose, and environment

   The purpose of this invention is to provide a suitable on-chip interface such that the original test suite can be used to test the embedded module. Both the presumption of accessibility and the requirement for real- time bus cycles are met in this structure.

Consider the invention's architecture as shown in Figure 1 which consists of embedded modules A and B with their normal (i.e., non-test mode) inter-module networks (nets). We will first consider only module A.

   If module A is of synchronous design, then the smallest meaningful time resolution to apply and observe signals at the embedded test points is the pulse width of one 50% duty cycle system clock. For example, we would divide a 4-clock real-time sequence into eight contiguous half-clock intervals to reproduce waveforms that were previously applied and observed by an external tester.

   The real-time signal requirement is met by first queueing the test data (inputs and expected outputs) for a real-time sequence in an on-chip FIFO (first-in, first-out) storage module. Referring to Figure 2, 3 and 4, the data for one real-time bus transaction is stored in the Virtual Pin (embedded test point) FIFO for each individ- ual pin.

   Between times when the real-time bus transactions are applied to the embedded test points, the module- under-test must be held in a benign suspended stale in order to process the data for the previous bus trans. action and refill the FIFO for the next bus transaction.

   Test data is presented to the embedded module and theoutput responses observed by negating the module suspension mechanism and then clocking the FIFO. Wait states (same data for...