Browse Prior Art Database

POWER SWITCHING CIRCUIT WITH LOW OFFSET VOLTAGE

IP.com Disclosure Number: IPCOM000005781D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2001-Nov-06
Document File: 2 page(s) / 95K

Publishing Venue

Motorola

Related People

David Overton: AUTHOR [+2]

Abstract

In some battery powered products, a secondary back-up cell is used to provide power to memory while the primary battery is being changed. A power switching circuit with low offset voltage and low current drain is needed to connect the memory to the back-up cell when the primary battery is removed and the supply voltage starts to drop.

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MOlVROLA Technical Developments Volume 9 August 1989

POWER SWITCHING CIRCUIT WITH LOW OFFSET VOLTAGE

by David Overton and Gary Pace

   In some battery powered products, a secondary back-up cell is used to provide power to memory while the primary battery is being changed. A power switching circuit with low offset voltage and low current drain is needed to connect the memory to the back-up cell when the primary battery is removed and the supply voltage starts to drop.

   The new powerswitchingcircuit shown in Figure 1 hasalow90mVoffsetvoltage,drawsvery littlestandby current in the "off" condition and is suitable for IC implementation. Power efficiency in the "on" condition is also very good. Referring to Figure 1, diode-connected pnp transistor 05 and bias current source Ibias provide a means to sense voltage V2. In a similar fashion, diode-connected transistorQ2 and bias current source lbiasl provide a means to sense voltage Vi. The output voltages of the Vl and V2 voltage sensing circuits, present at Q2 base/collector and Q5 base/collector, respectively, are applied to adifferential transconductance amplifier composed of pnp input transistors Q3 and Q4. The remaining transistors in the differential amplifier are npn transistors Q6, Q7, and Q8. The output current of the differential amplifier is supplied by the collector of Q8 and is applied to the base of pnp switching/regulatortransistorQi. The bias current I1 for the differential amplifier is set by resistor RI, current source Ibiasl, and the ratio of the emitter areas of Q2 and Q3 as well as the differen- tial voltage applied to the inputs of the differential amplifier. These circuit parameters have been chosen to make I1 =Ibiasl for the condition VI -V2=90 mV. The voltage drop across Rl is then approximately 36 mV. A 90 mV switch offset voltage was selected in order to keep transistor Ql out of hard collector-emitter saturation. Seventy- two millivolts of this offset voltage was achieved by making the emitter areas of transistors Q5 and Q2 ratio 4 to 1 and by making bias current lbiasl 4 ti...