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RECEIVER POWER CONSERVATION METHOD AND APPARATUS FOR RECEIVING A POCSAG SIGNAL

IP.com Disclosure Number: IPCOM000005792D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2001-Nov-07
Document File: 6 page(s) / 205K

Publishing Venue

Motorola

Related People

Michael J. DeLuca: AUTHOR

Abstract

This invention relates generally to the area of conservation of power in a receiver, and more particularly to a method and apparatus for conserving power during the reception of a POCSAG signal.

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MO7VROLA Technical Developments Volume 9 August 1989

RECEIVER POWER CONSERVATION METHOD AND APPARATUS FOR RECEIVING A POCSAG SIGNAL

by Michael J. DeLuca

This invention relates generally to the area of conservation of power in a receiver, and more particularly to a method and apparatus for conserving power during the reception of a POCSAG signal.

In order to improve the battery life performance of receivers such as portable battery powered pagers, it is desirable to conserve power whenever possible. The POCSAG paging protocol has a sync code which OCCW'S

periodically. The receiver of the present invention operates so as to conserve power during the POCSAG sync code.

   FIG. 1 shows a typical POCSAG protocol signal 10, and a power conservation strobe 20, used in prior art receivers. The sync code is a predetermined 32 bit binary word occurring at the beginning of a batch. Each batch has a sync code and eight frames of information. Each frame has two 32,21 BCH information words. The 32,21 BCH word allows both error detection and error correction. The processes of parity generating, error detecting and error correcting a 32,21 BCH word are well known to those of ordinary skill in the art.

   The receiver synchronizes to the POCSAG signal using processes well known to those of ordinary skill in the art. After acquiring sync, the receiver begins a batch decoding process wherein the receiver decodes in- formation within a preassigned frame which may include an address matching a preassigned address, in response to which the receiver would alert.

   Assume the receiveroperating per FIG. 1 has been preassigned to frame4. Having acquired sync, the receiver conserves power until the occurrence of frame 4. The receiver operates in a high power mode during frame 4 in order to decode information therein. Then the receiveroperates in a low power mode until the next sync code where the receiver again operates in a high power mode in order to receive the next sync code. When two con- secutive sync codes are missed, the receiver returns to the sync acquisition process.

   Figure 2 shows a block diagram of the paging receiver operating in accordance with the present invention. In the invention the 32,21 error detector is used by the sync maintenance function to determine of the signal is present. Figure 3 shows an overall flow chart for the synchronization to the POCSAG signal. In the presence of POCSAG signals the 32,21 words will be received with 0 or 1 bit errors. In response to this the paging receivem battery saves through the sync code. Prior art pagers consume power in order to rece...