Browse Prior Art Database

ADAPTIVE SYNTHESIZER DELAY

IP.com Disclosure Number: IPCOM000005813D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2001-Nov-08
Document File: 1 page(s) / 56K

Publishing Venue

Motorola

Related People

Joel Katz: AUTHOR

Abstract

The purposeof this invention is to decrease scan times by reducing the receive to receive time. The receive to transmit time can also be reduced in this manner. This can be accomplished by adapting the delays required after synthesizer programming to the frequency shift of the VCO. In addition, for the purpose of scan program- ming the receive frequencies in the scan list may be scanned in frequency order to minimize the frequency shift between the current channel and the next channel to be scanned. The ordering will not only allow shorter times to be used but will also decrease the synthesizer lock time in some cases.

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MOlVROLA Technical Developments Volume 9 August 1989

ADAPTIVE SYNTHESIZER DELAY

by Joel Katz

   The purposeof this invention is to decrease scan times by reducing the receive to receive time. The receive to transmit time can also be reduced in this manner. This can be accomplished by adapting the delays required after synthesizer programming to the frequency shift of the VCO. In addition, for the purpose of scan program- ming the receive frequencies in the scan list may be scanned in frequency order to minimize the frequency shift between the current channel and the next channel to be scanned. The ordering will not only allow shorter times to be used but will also decrease the synthesizer lock time in some cases.

   There are 3 delays associated with programming the synthesizer: Lock Time, Settle Time, and Load Pull Time. The settle time is the time it takes the synthesizer to come within 1 khz of the desired carrier frequency after locking. The load pull time is the time it takes the synthesizer to restabilize after the RFPA is turned on. This invention will decrease the settle time and the lock time. As the frequency shift increases the synthesizer settle time and lock time increase.

   The operation of the algorithm is as follows: If the last frequency ('N' counter value) programmed into the synthesizer is known and the current values to be programmed into the synthesizer is also known then from these values we can arrive at delta ('N' counter), which is directly propo...