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SMART ALLOCATE POLICY FOR ASSOCIATIVE COPY BACK CACHE

IP.com Disclosure Number: IPCOM000005845D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2001-Nov-12
Document File: 2 page(s) / 112K

Publishing Venue

Motorola

Related People

Robin Edenfield: AUTHOR [+3]

Abstract

The constantly increasing requirement for memory bandwidth by microprocessors has led to the widespread use of caches to provide a fast local memory. Furthermore, for data caches the use of a copy-back write policy is used to significantly reduce the number of writes to memory. This reduction is a result of the writes from the processor only going to the cache. The written or dirty cache entry is only written to main memorywhen that entry is chosen for replace- ment to make room for a new entry, or is specifically pushed out of the cache by a cache maintenance instruction. While the push for replacement by a new entry is normally transparent to processor activity, the push can generate an external bus error condition.

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MOTOROLA Technical Developments Volume 10 March 1990

SMART ALLOCATE POLICY FOR ASSOCIATIVE COPY BACK CACHE

by Robin Edenfield, Ralph McGarity and Russ Reininger

   The constantly increasing requirement for memory bandwidth by microprocessors has led to the widespread use of caches to provide a fast local memory. Furthermore, for data caches the use of a copy-back write policy is used to significantly reduce the number of writes to memory. This reduction is a result of the writes from the processor only going to the cache. The written or dirty cache entry is only written to main memorywhen that entry is chosen for replace- ment to make room for a new entry, or is specifically pushed out of the cache by a cache maintenance instruction. While the push for replacement by a new entry is normally transparent to processor activity, the push can generate an external bus error condition.

   An external bus error condition on the bus must cause exception processing because the push represents data which is not in memory, and can not get to memory because of the error. Because the push for replacement is not controlled by the processor, but by the cache controller, the push can happen during any processor operation, including exception processing (i.e. exception stacking, or tablewalking). If the push during exception processing also causes an exception (bus error), then at a minimum the processor has a much more difficult task since it must now handle two exceptions simultaneously. Since most processors can not handle multiple simultaneous faults a push bus error during exception processing normally will be an unrecoverable fault and the processor will halt.

   To avoid the problem with simultaneous exceptions some processor cache systems have exception memory ac- cesses for stacking or tablewalks bypass the cache entirely. This non-cachable mode for exception accesses is undesirable because it does not allow the processor to take advantage of the data cache. This can be a significant performance penalty because tablewalks and exception processing required for demand paging are not uncommon operations.

   We have proposed that the MC66040 processor, which has an internal copy-back data cache, both avoid the non- recoverable fault problem, and take advantage of the data cache during exception processing by using a smart alloca- tion policy during exception accesses to memory. A smart allocation policy means that the cache controller understands the different types of memory accesses (normal, exception, etc) and modifies it's repla...