Dismiss
There will be a system update on Friday, May 5th, 6 PM ET. You may experience a brief service interruption.
Browse Prior Art Database

CAPACITOR ELECTRODE FORMATION VIA EPITAXIAL LATERAL OVERGROWTH (ELO)

IP.com Disclosure Number: IPCOM000005870D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2001-Nov-13
Document File: 2 page(s) / 142K

Publishing Venue

Motorola

Related People

Mark D. Griswold: AUTHOR [+3]

Abstract

Epitaxial Lateral Overgrowth has been demonstrated to be aviable approach to solve future device isolation demands as well as holding promise for 3-dimensional integration [1,2,3,4,5,6]. EL0 is the process whereby silicon islands are created by depositing epitaxial silicon seeded in oxide openings (fig. 1.) and relying on the subsequent overgrowth of the epi with respect to the oxide window.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 50% of the total text.

Page 1 of 2

0 M

MO7VROLA Technical Developments Volume 10 March 1990

CAPACITOR ELECTRODE FORMATION VIA EPITAXIAL LATERAL OVERGROWTH (ELO)

by Mark D. Griswold, Shane R. Chilton and Frank R. Myers

   Epitaxial Lateral Overgrowth has been demonstrated to be aviable approach to solve future device isolation demands as well as holding promise for 3-dimensional integration [1,2,3,4,5,6]. EL0 is the process whereby silicon islands are created by depositing epitaxial silicon seeded in oxide openings (fig. 1.) and relying on the subsequent overgrowth of the epi with respect to the oxide window.

   Here Epitaxial Lateral Overgrowth is exploited to form the bottom electrode of a multiple poly capacitor. Specifically, this is applicable to devices which employ floating gates to realize non-volative memories such as EEPROMS and EPROMS. Non-volatile memories place stringent demands on interlevel dielectric (ILD) integrity and thickness control. The ILD serves to isolate the floating gate in any non-volatile device and must be fabricated in a manner such that dielectric breakdown, leakage, and thickness control are all optimal. Normally, the floating gate is manufactured via polysilicon deposition and subsequent doping. This process is the limiting factor for the interlevel formation. The ILD is usually formed exclusively via thermal oxidation, although stacked deposited dielectrics have been employed as well but with limited success. The quality of the ILD is related to the floating gate surface texture, impurity concentration, and impurity distribution. The surface texture controls ILD breakdown and leakage while the impurity concentration and distribution dictates oxide thickness control.

   Superior surface properties necessitate amorphous silicon deposition, high doping concentration, or more exten- sive poly annealing. All have been shown to degrade tunnel charge-dependent-breakdown and thereby limit array cycl- ing. Device scaling demands the ILD be fabricated as thin as possible, especially since EEPROM tunnel oxides will most likely not be reduced below 60 to 70 A. Polysilicon floating gates do not lend themselves to ILD thinning since thickness scaling and oxide breakdown/leakage are competing properties. The doping concentration must be maintain- ed at a high level to yield acceptable oxide leakage/breakdown properties yet,...