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SELF-MAINTAINING DATA TIME BASE CIRCUIT

IP.com Disclosure Number: IPCOM000005876D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2001-Nov-13
Document File: 1 page(s) / 57K

Publishing Venue

Motorola

Related People

Tim Laflin: AUTHOR

Abstract

In decoding synchronous data transmissions the receiving unit must be able to lock and maintain synchronization to the incoming signal. Most of the data decoding is done by microcomputer which has two major duties. The first is to acquire and maintain synchronization to the incoming signal. The second is to decode the incoming data. Both tasks are not a problem for most micmwmputers due to their speed of operation. The application of the diagram below is for low current operation devices (battery operated). If the burden of acquiring and maintaining synchronization is done by a phase locked loop in hardware external to the microcomputer, and an incoming bit rate clock is derived from this signal, it is possible to slow the microcomputers bus. The goal is to have the microcomputer run for as little time and as slowly as possible to achieve maximum battery life. By using the derived clock from the PLL and inputting it to a timer the microcomputer can be signaled after a programmed number of bit times have occurred. The reason this is so useful is because the microcomputer no longer needs to maintain synchronization to the data. The external PLL and timer can be used with a shift register to accumulate a programmed number of data bits while the computer works on other tasks. The microcomputer can now take larger quantities of information at a time. Previously the computer had to do all its work in a single bit time and also maintain synchronization to the data. Now the computer need not keep synchronization to the data and its data processing can be spread over the number of bits the external timer is set to, allowing the shift register to acquire the large strings of data. This method lets the microcomputer spread its processing over longer times and the computer gets fewer interrupts since it no longer maintains synchronization. This configuration can allow the computer lower its bus speed and save the large current drains produced by fast clocked microcomputers.

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MOTOROLA Technical Developments Volume 10 March 1990

SELF-MAINTAINING DATA TIME BASE CIRCUIT

by Tim Laflin

   In decoding synchronous data transmissions the receiving unit must be able to lock and maintain synchronization to the incoming signal. Most of the data decoding is done by microcomputer which has two major duties. The first is to acquire and maintain synchronization to the incoming signal. The second is to decode the incoming data. Both tasks are not a problem for most micmwmputers due to their speed of operation. The application of the diagram below is for low current operation devices (battery operated). If the burden of acquiring and maintaining synchronization is done by a phase locked loop in hardware external to the microcomputer, and an incoming bit rate clock is derived from this signal, it is possible to slow the microcomputers bus. The goal is to have the microcomputer run for as little time and as slowly as possible to achieve maximum battery life. By using the derived clock from the PLL and inputting it to a timer the microcomputer can be signaled after a programmed number of bit times have occurred. The reason this is so useful is because the microcomputer no longer needs to maintain synchronization to the data. The external PLL and timer can be used with a shift register to accumulate a programmed number of data bits while the computer works on other tasks. The microcomputer can now take larger quantities of information at a time. Previous...