Browse Prior Art Database

IMPROVED TONE DETECTOR

IP.com Disclosure Number: IPCOM000005878D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2001-Nov-13
Document File: 2 page(s) / 108K

Publishing Venue

Motorola

Related People

Richard A. Erhart: AUTHOR [+2]

Abstract

This paper describes a way to allow some simple hardware to be used to distinguish between very tightly spaced frequencies or tone signals. The hardware is purely digital in operation and can be programmed for a multitude of various tones with spacings as low as perhaps 5hz. This idea could also be used to distinguish between any tightly spaced baud rates for binary codes.

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MOTOROLA Technical Developments Volume 10 March 1990

IMPROVEDTONEDETECTOR

by Richard A. Erhart and Michael J. DeLuca

   This paper describes a way to allow some simple hardware to be used to distinguish between very tightly spaced frequencies or tone signals. The hardware is purely digital in operation and can be programmed for a multitude of various tones with spacings as low as perhaps 5hz. This idea could also be used to distinguish between any tightly spaced baud rates for binary codes.

   The idea would utilize a simple DPLL type bit synchronizer to attempt to lock on to a tone signal. The clock to run the DPLL must be a multiple of the desired tone. If many different tones are to be utilized by this same hardware then a frequency synthesizer can be used to provide a multiple of the desired input frequency. A lock detection algorithm can be applied to a small interval (16, 32, or 64 bits) of the incoming data while the bit sync is left running. The lock detector could indicate if the incoming frequency is even close to the desired tone, but it cannot detect very close fre- quency differences (less than 1%).

   The very close frequencies are distinguished in the following manner: If the Lock detector indicates a valid signal then the DPLL output clock is compared to a free running oscillator such as the synthesizer reference or the DPLL reference. The phase difference is recorded. Another interval is recieved and the process is repeated. Each interval is checked by the lock detector to determine if it is in a valid range of frequencies. At the end of each interval the DPLL output is compared to the free running oscillator. The key to this system is the comparison at the end of each interval which will tell you if the DPLL output is drifting from the free running clock.

   The true signal will not drift in phase to the free running clock (except for crystal tolerances), but all signals even with minimum frequency spacing will eventually phase drift away from the free running clock and can be detected. The tighter the frequency spacings, the more intervals must be analyzed to distinguish between the tones.

   This system will perform fine tuned differentiation of tones with hardware (or software) which is already available. The comparison of the phase error between the DPLL and the free running clock at the conclusion of each lock detec- tion interval is the key to the accuracy of this...