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Method for on-chip programmable power adjustment for thermal/electrical semiconductor component validation and manufacturing

IP.com Disclosure Number: IPCOM000005896D
Publication Date: 2001-Nov-14

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for an on-chip programmable power adjustment for thermal/electrical semiconductor component validation and manufacturing. Benefits include improved conformance to datasheet specifications, improved quality of the burn-in process, and quality and compatibility of original equipment manufacturer (OEM) platform solutions.

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Method for on-chip programmable power adjustment for thermal/electrical semiconductor component validation and manufacturing

Disclosed is a method for an on-chip programmable power adjustment for thermal/electrical semiconductor component validation and manufacturing. Benefits include improved conformance to datasheet specifications, improved quality of the burn-in process, and quality and compatibility of original equipment manufacturer (OEM) platform solutions.

Background

      During early platform thermal and electrical validation, designers utilize generated samples to validate that PC systems meet the thermal and electrical specifications of the product datasheet. Due to variations that exist in semiconductor manufacturing, a component utilized for system validation may not represent the 3-sigma specification for power, creating challenges for manufacturers and customers.

              Every microprocessor undergoes a manufacturing burn-in step. One of its challenges is the wide variation of silicon power at elevated (accelerated) voltages and temperatures. At these higher operating-stress conditions, subthreshold leakage power dominates power distribution. As a result, a wide range of power from 5W-40W occurs among microprocessors.

              Microprocessor manufacturers generate thousands of engineering and qualification samples for OEMs to develop and validate their PC platforms. To supply the OEMs with these samples, the manufacturer fabricates, sorts, assembles, burns in, and tests the components to revenue-like test conditions. The natural distribution of microprocessors is shipped to OEMs. In some cases, marketing specifically requests engineering to select microprocessors that are near the upper end of the power distribution. However, due to the availability of material and normal statistics, shipping units that meet or are very close to the data sheet specification for power is almost impossible. Of specific interest are the early engineering samples with power variation that is driven by fabrication process variations such as capacitance, resistance, and Le.

              For example, an OEM receives a microprocessor with a power of 70W (mean, median value of power) that has a datasheet specification of 75W. The OEM assumes that 70W is typical for that microprocessor and modifies and validates their platform solution to be stable at 70W. When high volume manufacturing starts, microprocessors ship at 75W, which might not work with the platform that was validated to 70W. This creates quality risks and brand image issues for both the OEM and the manufacturer.

Description

              The disclosed method is a circuit and an algorithm that are used during manufacturing and samples testing to tighten the power distribution so that validation of thermal and electrical solutions can be guaranteed to meet datasheet specification. The components of the disclosed method  are illustrated in Circuit 1 (see Figure 1). An application of the disclosed method is to maximize the distribution of power...