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SIMPLIFIED HIGH-SWING CASCODED CIRCUITS

IP.com Disclosure Number: IPCOM000005914D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2001-Nov-15
Document File: 2 page(s) / 110K

Publishing Venue

Motorola

Related People

Mathew A. Rybicki: AUTHOR

Abstract

A cascade connection of just two transistors realize high-swing, high-output impedance circuits in CMOS. This con- figuration can be applied to many different types of amplifiers, current sources and sinks and can be built using pro- cesses other than CMOS. The circuits works well in opamps and are designed to minimize area and power without losing performance.

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MOTOROLA Technical Developments Volume 10 March 1990

SIMPLIFIED HIGH-SWING CASCODED CIRCUITS

by Mathew A. Rybicki

Abstract

   A cascade connection of just two transistors realize high-swing, high-output impedance circuits in CMOS. This con- figuration can be applied to many different types of amplifiers, current sources and sinks and can be built using pro- cesses other than CMOS. The circuits works well in opamps and are designed to minimize area and power without losing performance.

Introduction

   Cascade connections of transistors have allowed higher gains to be achieved from amplifiers while reducing circuit complexity. These improvements come at little expense to the phase margin and thus stability of the closed-loop system. Circuit designers have progressively reduced the complexity of the bias circuitry required to bias the cascade device. The presented configuration attains the absolute limit of "no bias circuitry", while maintaining the same high-swing, high-output impedance feature that some of the later cascade designs offer.

   The amplifier presented in the Figure 1 below is a two transistor (Ml and M2), high-swing, cascade voltage amplifier which requires no bias circuitry. The two transistors are connected in series between, a current source from V,, and V,. The gates of the two transistors are tied together at the voltage input node of the amplifier. The wells of the tran- sistors are tied to their respective sources to prevent a bulk-to-source back-bias induced threshold voltage shift. If both devices are maintained in saturation, then high gain is achieved from Vin to Vout.

   The key design constraints of this circuit lie in the regulation of Vin and Vout, to maintain both transistors in satura- tion, and the sizing of the two transistors. Vin must be regulated such that Vout does not cause the drain-to-source voltage of Ml (Vdsl) to decrease below the drain saturation voltage of Ml (V,,,). Transistor Ml must be sized with a short- channel gate length to minimize its threshold voltage (I&). Transistor M2 must then be sized with a long-channel gate length to ensure that a difference in the two threshold voltages (I&-V") exist. Furthermore, the relative strength of Ml must be significantly greater than that of M2 to ensure that the differences in thresholds (I&V,,) are pronounced, as can be seen in equation (2). To ensure that both transistors are biased in saturation, Vd2 must be kept larger than the drain saturation voltage M2 (Vd&, that is:

Vdtat2 < Vd2 (1)

These constraints can be described algebraically. Assume that the current in Ml and M2 are qual to I, and that Ml and M2 have matching mobilities and gate oxide thicknesses. Combining Sah's equation for t...