Browse Prior Art Database

BUS REQUEST HOLD BY SOFTWARE

IP.com Disclosure Number: IPCOM000005957D
Original Publication Date: 1990-Oct-01
Included in the Prior Art Database: 2001-Nov-20
Document File: 2 page(s) / 99K

Publishing Venue

Motorola

Related People

Nathan Baron: AUTHOR

Abstract

This invention is an addition to commonly used bus arbitration protocol. The protocol works as follows: 1. Processor that needs access to the common bus asserts the BR (Bus Request) pin.

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MOTOROLA Technical Developments Volume 11 October 1990

BUS REQUEST HOLD BY SOFTWARE

by Nathan Baron

This invention is an addition to commonly used bus arbitration protocol.

The protocol works as follows:

1. Processor that needs access to the common bus asserts the BR (Bus Request) pin.

2. Bus arbitration unit asserts B6 (bus grant) pin when the bus is available.

3. BB (bus busy) pin is negated indicating that the bus is available. The processor asserts the BB pin and accesses the bus.

   4. If the current bus master does not use the bus it negates BR pin. This protocol allows the current bus master to "park" on the bus. In this state BR pin is negated but no other processor request the bus. The bus parking allows to lower bus arbitration overhead.

In time sensitive programs the current bus master would want to hold the bus mastership even if the bus is not currently accessed.

   This is done by asserting Bus Request Hold Control bit which forces BR pin to be aSserted unconditionally. In this case the current bus master will be able to hold the bus until the BRH control bit is negated. This approach allows bus mastership hold in a simple way using very little additional hardware inside the processor and using no additional hardware in bus arbitration unit.

This approach allows a very flexible arbitration because the bus arbitration unit can transfer bus mastership to other processor by negating B6 pin.

   The implementation of the invention lies entirely within one of the processors 1, 2. N of Figure 1. No modification of the bus arbitration unit is required, nor the arbitration scheme within that unit, nor the various bus request, bus grant and bus busy lines. The processor determines whether it is conducting operation of a time sensitive routine and will want the bus in a future instruction cycle (not necessarily the immediately following instruction cycle). If both these criteria are met, then the processor asserts its bus request pin by software. It maintains the signal on the bus request pin (mode) and so long as this signal is maintained, the bus arbitration unit will not pass bus grant on to any processor of tower priority Under these conditions, the processor is "parking" on the bus. Thus, the bus remains available to that pro- cessor for the instruction cycle when...