Browse Prior Art Database

HOST INTERFACE

IP.com Disclosure Number: IPCOM000005961D
Original Publication Date: 1990-Oct-01
Included in the Prior Art Database: 2001-Nov-20
Document File: 4 page(s) / 165K

Publishing Venue

Motorola

Related People

Sergio Liberman: AUTHOR [+4]

Abstract

Existing host interfaces do no allow for receipt of addresses. They allow data transfer only. This invention relates to a processor for connection to one or more other processors in a manner whereby the one or more other processors may access the on-chip memory of the first processor by treating the first processor as pure memory.

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MOTOROLA Technical Developments Volume 11 October 1990

HOST INTERFACE

by Sergio Liberman, Nathan Baron, Paul Marino and Elchanan Rushinek

Existing host interfaces do no allow for receipt of addresses. They allow data transfer only.

   This invention relates to a processor for connection to one or more other processors in a manner whereby the one or more other processors may access the on-chip memory of the first processor by treating the first processor as pure memory.

   In multiprocessing and linear processing systems, it is generally necessary when one processor wishes to write to the memory of another processor, for the first processor to write into a separate discrete memory, and for the other processor to read from that memory.

An interface is provided which eliminates the need for extra memory in the wmmunication between processors in a multi-processor system.

   The interface receives addresses from an external device and transfers data to and from that external device. The processor is interrupted sc as to allow data to be transferred to or from the processor's own memory, identified by an address received by the interface.

   The interface has wntml lines wmmon to the address bus, whereby signals received on the address bus are capable of being interpreted by the interface as instructions for operation of the interface. It comprises a known interface which allows data transfer only with the addition of address transfer capability in order to random access the processor's own memory.

   The interface comprises a host processor side on the left of Figure 1 and, on the right of the figure is shown the side corresponding to the other processor. Various registen are provided, as labelled on the figure. The overall function of the host interface is to enable receipt of a word on data bus 30, to treat this word as an address for addressing the internal memories of the host processor and to either write data from the data bus 30 into those memories or read data from those memories and output it on the data bus 30. For this to be achieved, it is necessary for the host interface to be able to read alternate words as addresses and data.

   The host processor sends a 32-bit address to an address bus common to the two processors. Four of these bits (A2-A5) are to be treated as instructions on instruction lines 32 and the remaining address bits are decoded by a decoder (not shown), which activates the host interface on host select (HS line). When such an address is received, the host interface control logic 40 generates an interrupt identified as write or read memory command which is sent to the pro cessor interrupt controller. The processor itself receives the interrupt from and enters a routine. While operation of the processor is suspended, a "write memory command" or "read memory command" may be executed as follows. These commands are new to the present invention, and are not to be found in the prior art.

   The "write memory command" flow is descri...