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A METHOD OF SYNCHRONIZING CLOCKS BETWEEN TWO CLOCK DOMAINS THAT HAVE A FIXED RELATIONSHIP TO EACH OTHER

IP.com Disclosure Number: IPCOM000005968D
Original Publication Date: 2001-Nov-20
Included in the Prior Art Database: 2001-Nov-20
Document File: 2 page(s) / 28K

Publishing Venue

Motorola

Related People

John D. Coddington: AUTHOR

Abstract

A METHOD OF SYNCHRONIZING CLOCKS BETWEEN TWO CLOCK DOMAINS THAT HAVE A FIXED RELATIONSHIP TO EACH OTHER

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A Method Of Synchronizing Clocks Between Two Clock Domains That Have A Fixed Relationship To Each Other

by John D. Coddington

This paper will discuss improvements to the synchronization of chipset clocks that are between different timing domains, that have a fixed relationship and are phased aligned by adding a counter. This method provides a useful way of synchronizing two chips or two functions in a System-On-a-Chip (SOC) environment.

This method can be easily extendible to two chips using the same core clock. It can also be used in the synchronization of two chips that are running off different ratios of two different phase aligned clocks.

This idea provides the framework to pass phase and ratio information between two chips in a chipset and use only one pin, and can also be extended to add a debug mode in case the clock generation logic of the chipset failed due to too much noise.

By adding a counter to count clocks between edges or pulses, the count can be used to determine the ratio and can create synching signals based of values of the count.  It is easily extendible to the higher clock ratios and can handle non-integer ratios.

The use of pulse generators on the clocks eliminates unknown timing of the falling edge due to a potential non-symmetric duty cycle. Only one signal is required to pass all the clocking information. The logic is fully static and can be synthesized, and the function of the logic can be simulated in normal tests using a logic simulator.

In the half-clock generation logic, a counter counts through zero and resets to zero. The interface for the two chips may be...