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A Unified and Flexible Priority Scheme for Controlling a Write Buffer

IP.com Disclosure Number: IPCOM000005969D
Original Publication Date: 2001-Nov-20
Included in the Prior Art Database: 2001-Nov-20
Document File: 4 page(s) / 34K

Publishing Venue

Motorola

Related People

Afzal Malik: AUTHOR [+2]

Abstract

Next generation portable devices are placing stringent requirements on overall system power and performance. Voice recognition, streaming video and high speed wireless internet access are just some of the features being incorporated in these handheld electronic gadgets. Therefore, some processors have been designed for high performance and cost sensitive portable products as well as for high end embedded control applications. For example, one such processor integrates a unified 16KB cache, and additional instruction pipelining and buffering to increase the operating frequency. An 8-entry write buffer which can defer pending write misses and writethrough accesses is used in order to maximize performance. In this paper, we discuss the flexible priority scheme for controlling the write buffer. We use a hardware technique which provides a flexible mechanism to control emptying and flushing of write buffer based on a set of configurable thresholds, as well as a mechanism to alter the priorities from the write buffer to the main memory system. The same unified mechanism is used to support flushing as well as providing a solution for the read after write (RAW) hazard avoidance.

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A Unified and Flexible Priority Scheme for Controlling a Write Buffer

Afzal Malik, Bill Moyer

    Embedded Platform Solutions, Motorola, Inc. 7700 West Parmer Lane, Building C, Austin TX 78729 {malik,billm}@eps.sps.mot.com

Abstract

   Next generation portable devices are placing stringent requirements on overall system power and performance. Voice recognition, streaming video and high speed wireless internet access are just some of the features being incorpo- rated in these handheld electronic gadgets. Therefore, some processors have been designed for high performance and cost sensitive portable products as well as for high end embedded control applications. For example, one such pro- cessor integrates a unified 16KB cache, and additional instruction pipelining and buffering to increase the operat- ing frequency. An 8-entry write buffer which can defer pending write misses and writethrough accesses is used in order to maximize performance. In this paper, we discuss the flexible priority scheme for controlling the write buffer. We use a hardware technique which provides a flexible mechanism to control emptying and flushing of write buffer based on a set of configurable thresholds, as well as a mechanism to alter the priorities from the write buffer to the main memory system. The same unified mechanism is used to support flushing as well as providing a solution for the read after write (RAW) hazard avoidance.

Additionally, control for flushing the buffer must be pro- vided, as well as hazard prevention logic for avoiding read after write (RAW) data hazards.

  Our write buffer implementation provides a flexible mechanism to control emptying and flushing of entries based on a set of configurable thresholds, as well as a mechanism to alter the priorities. The same unified mecha- nism is used to support buffer flushing as well as providing a solution for the RAW hazard avoidance.

  In case of the write buffer, a primary advantage of our implementation is the unification of support for multiple control functions by utilizing a set of selectable (as well as programmable) thresholds.

2 Writethrough Mode

  Write accesses can be marked as writethrough by a Memory Management Unit or a write mode bit in a Cache Control Register (CACR). In either case, writethrough writes are always passed on to the external bus. This mode of operation is desirable in systems such as those with shared memory (coherency concerns) or external memory drives.

  The obvious downfall with writethrough writes is the processor stall issue due to external memory latency. To avoid this latency issue, a processor may utilize a FIFO write buffer.

  Writes in writethrough mode that miss in the cache are written to the external bus, but do not cause the corre- sponding line in the memory to be loaded into the cache. Write accesses that hit always write through to memory and update the corresponding cache line.

1 Introduction

  Write buffers are used in high performance micropro- cessor to enab...