Browse Prior Art Database

ADDRESS DEPENDENT BIT ERROR CORRECTION

IP.com Disclosure Number: IPCOM000005993D
Original Publication Date: 1990-Oct-01
Included in the Prior Art Database: 2001-Nov-22
Document File: 1 page(s) / 68K

Publishing Venue

Motorola

Related People

Mike DeLuca: AUTHOR [+2]

Abstract

This invention relates to a POCSAG address bit error wrrection method for use in a pager. The invention provides for each address to have a unique number of allowable bit errors. Since it is possible to determine which of the ad- dresses are likely to false on a particular customer's implementation of POCSAG, falsing addresses can be programmed to 0 or 1 bit errors, thereby reducing the probability of falsely decoding the address while also reducing the sensitivity of the address. Addresses not likely to false can use the normal address correction (2 bits) and maintain normal sen- sitivity. This invention may have application to other paging protocols such as ERMES, Golay, etc.

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MOTOROLA Technical Developments Volume 11 October 1990

ADDRESS DEPENDENT BIT ERROR CORRECTION

by Mike DeLuca and David Hayes

   This invention relates to a POCSAG address bit error wrrection method for use in a pager. The invention provides for each address to have a unique number of allowable bit errors. Since it is possible to determine which of the ad- dresses are likely to false on a particular customer's implementation of POCSAG, falsing addresses can be programmed to 0 or 1 bit errors, thereby reducing the probability of falsely decoding the address while also reducing the sensitivity of the address. Addresses not likely to false can use the normal address correction (2 bits) and maintain normal sen- sitivity. This invention may have application to other paging protocols such as ERMES, Golay, etc.

   An example of the need for this invention arose in a particular implementation of POCSAG where the POCSAG batch was terminated with 300 bps 1-O pattern. Certain pager addresses would incorrectly decode the 300 bps 1-O pattern as their correct address, When considering that POCSAG addresses allows for 2 bit error correction, it was determined that 19 valid addresses would be detected within 2 bit errors. Then considering that the data is sampled with a DPLL which may adjust on every transition, an additional 6 valid POCSAG addresses would be detected within 1 bit error, and an additional 48 addresses would be detected within 2 bit errors. Thus for these 64 identif...