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HIGH RESOLUTION OVERSAMPLING BIT SYNC ALGORITHM (LOW PAGER OVERSAMPLING BIT SYNC ALGORITHM)

IP.com Disclosure Number: IPCOM000006026D
Original Publication Date: 1990-Oct-01
Included in the Prior Art Database: 2001-Nov-27
Document File: 3 page(s) / 122K

Publishing Venue

Motorola

Related People

Warren Glotzbach: AUTHOR [+3]

Abstract

Oversampling bit sync algorithms typically have a resolution that is equal to or less than the oversampling clock period. This means that if the oversampling clock were eight times the bit time then the algorithm would find the center of the bit to within one eighth of a bit or worse (114, 112). By employing a method that finds an edge of a bit on one phase of the oversampling clock and the center of a bit on the other phase of the oversampling clock a resolution of twice the oversampling clock can be realized. This means that if an oversampling clock of eight times the bit time is used then the algorithm will find the center of the bit to within one sixteenth of a bit or twice the resolution of the over- sampling clock. For a given required resolution, lower power can be achieved because the clock rate can be reduced by half and the desired resolution can still be achieved.

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Technical Developments Volume 11 October 1990

HIGH RESOLUTION OVERSAMPLING BIT SYNC ALGORITHM

(LOW PAGER OVERSAMPLING BIT SYNC ALGORITHM)

by Warren Glotzbach, Zaffer Merchant and Doug Ayerst

   Oversampling bit sync algorithms typically have a resolution that is equal to or less than the oversampling clock period. This means that if the oversampling clock were eight times the bit time then the algorithm would find the center of the bit to within one eighth of a bit or worse (114, 112). By employing a method that finds an edge of a bit on one phase of the oversampling clock and the center of a bit on the other phase of the oversampling clock a resolution of twice the oversampling clock can be realized. This means that if an oversampling clock of eight times the bit time is used then the algorithm will find the center of the bit to within one sixteenth of a bit or twice the resolution of the over- sampling clock. For a given required resolution, lower power can be achieved because the clock rate can be reduced by half and the desired resolution can still be achieved.

   To accomplish this requires a means of detecting the bit transition and some bit sampling storage (fig. l.l), a sample counter with output decoding (fig 1.2) and a state machine which makes decisions on when the edge occurs and when to take the center sample (fig. 1.3).

   In the case of our scenario an edge detector will detect the transition between logic levels. The sampling clock in this scenario is chosen to be 8 times the bit time or 8 samples per bit. The edge detector and sample counter must be clocked on one phase of the sample clock and the state machine must be clocked on the other phase of the sample clock. This can easily be accomplished by inverting the sample clock (fig. 2). Using these elements a center bit sample resolution of 1118 of a bit can be realized.

   Referring to fig. 2 shows the sample clock (SCLK), the inverted sample clock (/SCLK), counter value, transition points of the circuitry, over sample and center sample points and two data bits. A worst case example occurs when a data transition is aligned with an over-sample point, Hardware circuit transitions and state machine transitions will oc- cur on the rising edges of SCLK and /SCLK respectively.

   It is assumed at the start of the example that both the current sample and previous sample flip flops in fig. 11 hold the value of 0 to represent the samples before point...