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AN ALIGNMENT-TOLERANT CONTACT PROCESS USING LANDING PADS

IP.com Disclosure Number: IPCOM000006046D
Original Publication Date: 1991-Apr-01
Included in the Prior Art Database: 2001-Nov-28
Document File: 2 page(s) / 103K

Publishing Venue

Motorola

Related People

Yee-Chaung See: AUTHOR [+2]

Abstract

As VLSI process technology advances, registration requirements become more stringent. These requirements are particularly important in applications with a large chip size such as microprocessors, megabit density memories where competitive cell size is critical, and high density gate arrays. One can achieve better registration through either improved registration capability using more advanced optical aligners or through innovative process techniques. The former approach is not only expensive but also more difficult because the improvement in registration capability of new equipment has not progressed at the same rate as the scaling of sub-micron feature sizes.

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MOIOROLA INC. Technical Developments Volume 12 April 1991

AN ALIGNMENT-TOLERANT CONTACT PROCESS USING LANDING PADS

by Yee-Chaung See and Rick Sivan

   As VLSI process technology advances, registration requirements become more stringent. These requirements are particularly important in applications with a large chip size such as microprocessors, megabit density memories where competitive cell size is critical, and high density gate arrays. One can achieve better registration through either improved registration capability using more advanced optical aligners or through innovative process techniques. The former approach is not only expensive but also more difficult because the improvement in registration capability of new equipment has not progressed at the same rate as the scaling of sub-micron feature sizes.

  One example of achieving better registration tolerance through innovative process techniques is to use conductive "landing pads" to relax the contact registration requirement from the gate polysilicon. Metal to diffusion contacts in an SRAM cell often are adjacent to a poly gate on one side and to the field oxide on another. The minimum separation of the contact edge to this poly edge must take into account the hvo registration errors of aligning this contact to the active area and to the gate area, plus the variations in critical dimension of these two layers; When tapered contacts are formed, an additional provision must also be made to prevent the tapered contact walls from exposing the gate poly. This problem can be alleviated by opening intermediate (window) contacts to diffusions then depositing and patterning the conductive thin film to form a landing pad around the window contact opening. An example of this technique is outlined in more detail as follows.

After the gate pattern is defined by a composite layer of a thin dielectric (silicon nitride or oxide) on

top of doped polysilicon, another dielectric (oxide or nitride) of an appropriate thickness (e.g. 15008, to 3000A) is deposited. A reactive ion etch process forms the sidewall spacer and exposes the active area of the source/drain regions. The combinatio...