Browse Prior Art Database

RADIATION HARDENING FOR LOCOS WITH SALICIDE

IP.com Disclosure Number: IPCOM000006145D
Original Publication Date: 1991-Apr-01
Included in the Prior Art Database: 2001-Dec-07
Document File: 2 page(s) / 126K

Publishing Venue

Motorola

Related People

Clarence L. Lund: AUTHOR [+3]

Abstract

Behavior of semiconductor devices can be altered significantly by exposure to ionizing radiation. Dur- ing irradiation, electron-hole pairs are generated in the semiconductor, and in any dielectrics used, such as isolation or gate oxides. Charge generated in the dielectric can become a particular problem. While the generated electrons are swept out of the dielectric and recombine fairly rapidly, the less mobile holes remain, causing a build up of positive charge. For a PMOS device, this charge build up results in, among other effects, higher device and field thresholds. In the NMOS device, however, this charge tends to lower the device threshold, plus can also create a parasitic n- channel in the P- well under the field oxide, shorting the Nt source and drains to the N-well or substrate.

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MOTOROLA INC. Technical Developments Volume 12 April 1991

RADIATION HARDENING FOR :

LOCOS WITH SALICIDE ;,

by Clarence L. Lund, Jenny M. Ford and Francine Y. Robb

  Behavior of semiconductor devices can be altered significantly by exposure to ionizing radiation. Dur- ing irradiation, electron-hole pairs are generated in the semiconductor, and in any dielectrics used, such as isolation or gate oxides. Charge generated in the dielectric can become a particular problem. While the generated electrons are swept out of the dielectric and recombine fairly rapidly, the less mobile holes remain, causing a build up of positive charge. For a PMOS device, this charge build up results in, among other effects, higher device and field thresholds. In the NMOS device, however, this charge tends to lower the device threshold, plus can also create a parasitic n- channel in the P- well under the field oxide, shorting the Nt source and drains to the N-well or substrate.

  One method of improving radiation hardness of CMOS circuits is by the addition of Pt guard rings, as illustrated in Figure l(a). The guard ring spaces the Nt regions away from the edge of the isolation dielectric and increases the immunity of the circuit to radiation by increasing the total dose required to invert the P- well in that region. Unfortunately, the com- monly used method of forming these guard rings is not compatible with an important feature of many high performance CMOS technologies: a low resistance gate and source/drain shunt to reduce the parasitic resistance in the device. The commonly used shunt is a metal salicide, and all exposed silicon is covered with a low resistance material, independent of whether the silicon is doped p and n type. As shown in Figure. l(b), if the conventional structure is salicide, the N+ source/drain is shorted to the guard ring, rendering the device inoperable.

  This problem cannot be solved by the simple deposition of an etchable layer on the wafer to form and protect the guard from the shunt, since such a layer would also prohibit formation of the salicide on the polysilicon gate at the edge of the Nt source/drain. In advance CMOS technologies, where diodes are

formed in the polysilico?, the salicide must cover the poly in that area, to insure that the Pt and Nt poly are shorted together. A thick oxide OT other barrier prior to gate poly deposition cannot be used either, since if the oxide under the gate' is too thick, the guard ring will not be effective since the P- well will invert easily.

  The invention detailed here describes an alternate integration scheme which enables fabrication of guard rings on LOCOS isolateb CMOS even with...